Interrupt Control - Renesas M16C/29 Series Hardware Manual

M16C/29 Group

9.3 Interrupt Control

The following describes how to enable/disable the maskable interrupts, and how to set the priority in
which order they are accepted. What is explained here does not apply to nonmaskable interrupts.
Use the FLG register's I flag, IPL, and each interrupt control register's ILVL2 to ILVL0 bits to enable/
disable the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each
interrupt control register.
Figure 9.3.1 shows the interrupt control registers.
Also, the following interrupts share a vector and an interrupt control register.
________
•INT4 and SIO3
________
•INT5 and SIO4
•A/D converter and Key input interrupt
•ICOC base timer and S
•ICOC interrupt 1 and I
An interrupt request is set by the IFSR6, IFSR7 bits in the IFSR register and the IFSR21, IFSR26 and
IFSR27 bits in the IFSR2A register. Figure 9.3.2 shows the IFSR, IFSR2A registers.
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
/S
CL DA
2
C bus interface
page 66 of 402
9. Interrupts