Renesas M16C/29 Series Hardware Manual page 13

19.2 Port Pi Register (Pi Register, i = 0 to 3, 6 to 10) ......................................................... 309
19.3 Pull-up Control Register 0 to Pull-up Control Register 2 (PUR0 to PUR2 Registers) ..... 309
19.4 Port Control Register .................................................................................................. 309
19.5 Pin Assignment Control register (PACR) .................................................................... 310
19.6 Digital Debounce function ........................................................................................... 310
20. Electrical Characteristics ............................................................................323
20.1. Normal version .......................................................................................................... 323
20.2. T version .................................................................................................................... 344
21. Flash Memory Version ...............................................................................365
21.1 Flash Memory Performance ....................................................................................... 365
21.2 Memory Map ............................................................................................................... 367
21.3 Functions To Prevent Flash Memory from Rewriting .................................................. 370
21.3.1 ROM Code Protect Function ................................................................................ 370
21.3.2 ID Code Check Function ...................................................................................... 370
21.4 CPU Rewrite Mode ..................................................................................................... 372
21.4.1 EW0 Mode ........................................................................................................... 373
21.4.2 EW1 Mode ........................................................................................................... 373
21.5 Register Description ................................................................................................... 374
21.5.1 Flash memory control register 0 (FMR0): ............................................................ 374
•FMR 00 Bit .................................................................................................................. 374
•FMR01 Bit ................................................................................................................... 374
•FMR02 Bit ................................................................................................................... 374
•FMSTP Bit .................................................................................................................. 374
•FMR06 Bit ................................................................................................................... 374
•FMR07 Bit ................................................................................................................... 374
21.5.2 Flash memory control register 1 (FMR1): ............................................................ 375
•FMR11 Bit ................................................................................................................... 375
•FMR16 Bit ................................................................................................................... 375
•FMR17 Bit ................................................................................................................... 375
21.5.3 Flash memory control register 4 (FMR4): ............................................................ 375
•FMR40 Bit ................................................................................................................... 375
•FMR41 Bit ................................................................................................................... 375
•FMR46 Bit ................................................................................................................... 375
21.6 Precautions in CPU Rewrite Mode ............................................................................. 380
21.6.1 Operation Speed .................................................................................................. 380
21.6.2 Prohibited Instructions .......................................................................................... 380
21.6.3 Interrupts .............................................................................................................. 380
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