Renesas M16C/29 Series Hardware Manual page 223

M16C/29 Group
(1) U2SMR register ABSCS bit (bus collision detect sampling clock select)
Transfer clock
TxD2
RxD2
Timer Aj
Timer Aj: timer A0 when UART2
(2) U2SMR register ACSE bit (auto clear of transmit enable bit)
Transfer clock
TxD2
RxD2
U2BCNIC register
IR bit (Note)
U2C1 register
TE bit
Note: BCNIC register when UART2.
(3) U2SMR register SSS bit (Transmit start condition select)
If SSS bit = 0, the serial I/O starts sending data one transfer clock cycle after the transmission enable condition is met.
Transfer clock
TxD2
Transmission enable condition is met
If SSS bit = 1, the serial I/O starts sending data at the rising edge (Note 1) of RxD2
CLK2
TxD2
RxD2
Note 1: The falling edge of RxD2 when IOPOL=0; the rising edge of RxD2 when IOPOL = 1.
Note 2: The transmit condition must be met before the falling edge (Note 1) of RxD.
This diagram applies to the case where IOPOL=1 (reversed).
Figure 14.1.5.1. Bus Collision Detect Function-Related Bits
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
If ABSCS=0, bus collision is determined at the rising edge of the transfer clock
ST D0
Input to TAj
IN
ST D0
ST D0
ST D0
(Note 2)
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14.1.5 Special Mode 3 (IEBus Mode) (UART2)
D1 D2 D3 D4
If ABSCS=1, bus collision is determined when timer
Aj (one-shot timer mode) underflows.
D1 D2 D3 D4
D1 D2 D3 D4
D1 D2 D3 D4
D5 D6 D7 D8
D5 D6 D7 D8
If ACSE bit = 1 (automatically
clear when bus collision occurs),
the TE bit is cleared to 0
(transmission disabled) when
the U2BCNIC register s IR bit = 1
(unmatching detected).
D5 D6 D7 D8
D5 D6 D7 D8
SP
SP
SP
SP