Renesas M16C/29 Series Hardware Manual page 76

16-bit single-chip microcomputer
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M16C/29 Group
Table 7.6.1. Allowed Transition and Setting
High-speed mode,
middle-speed mode
Low-speed mode 2
Low power dissipation
mode
PLL operation mode 2
On-chip oscillator mode
On-chip oscillator
low power dissipation
mode
Stop mode
Wait mode
Notes:
1. Avoid making a transition when the CM21 bit is set to "1" (oscillation stop, re-oscillation detection function enabled).
Set the CM21 bit to "0" (oscillation stop, re-oscillation detection function disabled) before transiting.
2. On-chip oscillator clock oscillates and stops in low-speed mode. In this mode, the on-chip oscillator can be used as peripheral function clock.
Sub clock oscillates and stops in PLL operation mode. In this mode, sub clock can be used as peripheral function clock.
3. PLL operation mode can only be entered from and changed to high-speed mode.
4. Set the CM06 bit to "1" (division by 8 mode) before transiting from on-chip oscillator mode to high- or middle-speed mode.
5. When exiting stop mode, the CM06 bit is set to "1" (division by 8 mode).
6. If the CM05 bit is set to "1" (main clock stop), then the CM06 bit is set to "1" (division by 8 mode).
7. A transition can be made only when sub clock is oscillating.
8. State transitions within the same mode (divide-by-n values changed or subclock oscillation turned on or off) are shown in the table below.
Divided
No
by 2
division
(4)
No division
Divided by 2
(3)
(3)
(4)
Divided by 4
(3)
(4)
Divided by 8
(3)
(4)
Divided by 16
(2)
--
No division
Divided by 2
--
(2)
--
--
Divided by 4
--
--
Divided by 8
--
--
Divided by 16
9. ( ) : setting method. Refer to following table.
Setting
(1)
CM04 = 0
Sub clock turned off
(2)
CM04 = 1
Sub clock oscillating
CM06 = 0,
(3)
CPU clock no division mode
CM17 = 0 , CM16 = 0
CM06 = 0,
(4)
CPU clock division by 2 mode
CM17 = 0 , CM16 = 1
CM06 = 0,
(5)
CPU clock division by 4 mode
CM17 = 1 , CM16 = 0
CM06 = 0,
(6)
CPU clock division by 16 mode
CM17 = 1 , CM16 = 1
(7)
CPU clock division by 8 mode
CM06 = 1
Main clock, PLL clock,
(8)
CM07 = 0
or on-chip oscillator clock selected
(9)
CM07 = 1
Sub clock selected
(10)
CM05 = 0
Main clock oscillating
(11)
CM05 = 1
Main clock turned off
PLC07 = 0,
(12)
Main clock selected
CM11 = 0
PLC07 = 1,
(13)
PLL clock selected
CM11 = 1
(14)
CM21 = 0
Main clock or PLL clock selected
(15)
CM21 = 1
On-chip oscillator clock selected
(16)
CM10 = 1
Transition to stop mode
(17)
wait instruction
Transition to wait mode
(18)
Exit stop mode or wait mode
Hardware interrupt
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
High-speed mode,
Low-speed mode 2
Low power
middle-speed mode
dissipation mode
(9) 7
8
See Table A
(8)
--
(10)
(12) 3
--
(14) 4
--
--
--
(18) 5
(18)
(18)
(18)
Sub clock oscillating
Divided
Divided
Divided
No
by 8
by 16
by 4
division
(5)
(7)
(6)
(1)
(5)
(7)
(6)
--
(7)
(6)
--
(5)
(6)
--
(5)
(7)
--
--
--
--
--
--
--
(3)
(2)
--
--
(3)
--
(2)
--
(3)
--
--
(2)
(3)
Operation
page 56 of 402
State after transition
On-chip oscillator
PLL operation
mode 2
mode
(13) 3
--
(11) 1, 6
--
--
--
--
--
See Table A
--
--
(18)
--
(18)
--
Sub clock turned off
Divided
Divided
Divided
Divided
by 2
by 4
by 8
by 16
--
--
--
--
(1)
--
--
--
--
(1)
--
--
--
--
(1)
--
--
--
--
(1)
(4)
(5)
(7)
(6)
(5)
(7)
(6)
(4)
(7)
(6)
(4)
(5)
(6)
(4)
(5)
(7)
--: Cannot transit
CM04, CM05, CM06, CM07 : bit of CM0 register
CM10, CM11, CM16, CM17 : bit of CM1 register
CM20, CM21
: bit of CM2 register
PLC07
: bit of PLC0 register
7. Clock Generation Circuit
On-chip oscillator
low power
Stop mode
dissipation mode
(16) 1
(15)
--
(16) 1
--
--
(16) 1
--
--
--
--
--
(11) 1
(16) 1
8
(16) 1
8
(10)
See Table A
(18) 5
(18) 5
(18)
(18)
--
Wait mode
(17)
(17)
(17)
--
(17)
(17)
--
--: Cannot transit

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