Renesas M16C/29 Series Hardware Manual page 458

M16C/29 Group
1.11 Precautions for CAN Module
1.11.1 Reading C0STR Register
The CAN module on the M16C/29 group updates the status of the C0STR register in a certain period.
When the CPU and the CAN module access to the C0STR register at the same time, the CPU has the
access priority; the access from the CAN module is disabled. Consequently, when the updating period of
the CAN module matches the access period from the CPU, the status of the CAN module cannot be
updated. (See Figure 1.11.1.)
Accordingly, be careful about the following points so that the access period from the CPU should not
match the updating period of the CAN module:
(1) There should be a wait time of 3f
register. (See Figure 1.11.2.)
(2) When the CPU polls the C0STR register, the polling period must be 3f
1.11.3.)
Table 1.11.1 CAN Module Status Updating Period
3f period = 3
CAN
(Example 1) Condition X
(Example 2) Condition X
(Example 3) Condition X
(Example 4) Condition X
(Example 5) Condition X
Rev.1.00 Nov 01,2004
REJXXXXXXX-0100Z
CAN
X (Original oscillation period)
IN
16 MHz CCLK: Divided by 1
IN
16 MHz CCLK: Divided by 2
IN
16 MHz CCLK: Divided by 4
IN
16 MHz CCLK: Divided by 8
IN
16 MHz CCLK: Divided by 16
IN
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or longer (see Table 1.11.1) before the CPU reads the C0STR
Division value of the CAN clock (CCLK)
3f
CAN
3f
CAN
3f
CAN
3f
CAN
3f
CAN
or longer. (See Figure
CAN
period = 3 62.5 ns
period = 3 62.5 ns
period = 3 62.5 ns
period = 3 62.5 ns
period = 3 62.5 ns
1 = 187.5 ns
2 = 375 ns
4 = 750 ns
8 = 1.5 µs
16 = 3 µs