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M16C/29 Group
Figure 13.1 shows the block diagram of the IC/OC.
BCK1 to BCK0
11
f
or f
1
2
Two-phase
10
pulse input
Digital
INPC1
0
filter
Digital
INPC1
1
filter
Digital
INPC1
2
filter
Digital
INPC1
3
filter
Digital
INPC1
4
filter
Digital
INPC1
5
filter
Digital
INPC1
6
filter
Digital
Digital
INPC1
7
filter
debounce
Figures 13.1. IC/OC Block Diagram
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
Main clock,
PLL clock,
On-chip
oscillator clock
Request by matching G1BTRR and base timer
Request by matching G1PO0 register and base timer
Request from INT1 pin
BTS
(n+1)
Divider register
(G1DV)
00
10:f
BT1
Edge
11: f
or f
1
2
select
DF1 to DF0
CTS1 to CTS0
00
10:f
BT1
Edge
11: f
or f
1
2
select
DF1 to DF0
CTS1 to CTS0
00
10:f
BT1
11: f
or f
Edge
1
2
select
DF1 to DF0
CTS1 to CTS0
00
10:f
BT1
11: f
or f
1
2
Edge
select
DF1 to DF0
CTS1 to CTS0
00
10:f
BT1
11: f
or f
Edge
1
2
select
DF1 to DF0
CTS1 to CTS0
00
10:f
BT1
11: f
or f
1
2
Edge
select
DF1 to DF0
CTS1 to CTS0
00
10:f
BT1
11: f
or f
1
2
Edge
Gate
1
select
function
DF1 to DF0
GT
CTS1 to CTS0
00
10:f
BT1
11: f
or f
1
2
Edge
Gate
1
select
function
DF1 to DF0
GT
CTS1 to CTS0
page 133 of 402
13. Timer S (Input Capture / Output Compare)
PCLK0=0
1/2
f
1
PCLK0=1
Base timer reset
f
BT1
Base timer reset
register (G1BTRR)
G1TM0, G1PO0
register
G1TM1, G1PO1
register
G1TM2, G1PO2
register
G1TM3, G1PO3
register
G1TM4, G1PO4
register
G1TM5, G1PO5
register
0
0
G1TM6, G1PO6
Prescaler
1
function
register
PR
0
0
Prescaler
1
function
PR
BCK1 to BCK0 : Bits in the G1BCR0 register
BTS: Bits in the G1BCR1 register
CTS1 to CTS0, DF1 to DF0, GT, PR : Bits in the G1TMCRj register (j= 0 to 7)
PCLK0 : Bits in the PCLKR register
or f
2
Base timer
Base timer over flow request
Base timer interrupt request
Base timer reset request
(Note 1)
PWM
output
PWM
output
PWM
output
PWM
output
OUTC1
0
OUTC1
1
OUTC1
2
OUTC1
3
OUTC1
4
OUTC1
5
OUTC1
6
OUTC1
7
Ch0 to ch7 to Interrupt
Request Register
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