Renesas M16C/29 Series Hardware Manual page 93

M16C/29 Group
The operation of saving registers carried out in the interrupt sequence is dependent on whether the
(Note)
SP , at the time of acceptance of an interrupt request, is even or odd. If the stack pointer
even, the FLG register and the PC are saved, 16 bits at a time. If odd, they are saved in two steps, 8
bits at a time. Figure 9.4.3.2 shows the operation of the saving registers.
Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the SP
indicated by the U flag. Otherwise, it is the ISP.
(1) SP contains even number
Address
[SP] – 5 (Odd)
[SP] – 4 (Even)
[SP] – 3(Odd)
[SP] – 2 (Even)
[SP] – 1(Odd)
[SP] (Even)
(2) SP contains odd number
Address
[SP] – 5 (Even)
[SP] – 4(Odd)
[SP] – 3 (Even)
[SP] – 2(Odd)
[SP] – 1 (Even)
[SP] (Odd)
Note: [SP] denotes the initial value of the SP when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Figure 9.4.3.2. Operation of Saving Register
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
Stack
PC
L
PC
M
FLG
L
FLG PC
H
Stack
PC
L
PC
M
FLG
L
FLG PC
H
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Sequence in which order
registers are saved
(2) Saved simultaneously,
all 16 bits
(1) Saved simultaneously,
all 16 bits
H
Finished saving registers
in two operations.
Sequence in which order
registers are saved
(3)
(4)
Saved, 8 bits at a time
(1)
(2)
H
Finished saving registers
in four operations.
9. Interrupts
(Note)
is