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M16C/29 Group
No reverse
RxD data
RxD2
reverse circuit
1SP
STPS=0
SP
STPS=1
2SP
2SP
SP
SP
1SP
Figure 14.1.3. Block diagram of UART2 transmit/receive unit
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
IOPOL=0
IOPOL=1
Reverse
PAR
disabled
Clock
synchronous
PRYE=0
type
SP
PAR
PRYE=1
PAR
UART
enabled
0
0
0
0
0
PAR
enabled
STPS=1
UART
PRYE=1
PAR
STPS=0
PRYE=0
Clock
synchronous
type
PAR
disabled
0
page 166 of 402
Clock
synchronous type
UART
(7 bits)
UART
UART(7 bits)
(8 bits)
Clock
UART
synchronous type
(9 bits)
UART
(8 bits)
UART
(9 bits)
0
0
D
D
D
8
7
6
Logic reverse circuit + MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
Logic reverse circuit + MSB/LSB conversion circuit
D
D
D
7
6
8
UART
(8 bits)
UART
(9 bits)
UART
Clock
(9 bits)
synchronous type
UART
UART(7 bits)
(7 bits)
UART
(8 bits)
Clock
synchronous type
U2ERE
=0
U2ERE
=1
SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR : U2MR register's bit
U2ERE : U2C1 register's bit
14.1 UARTi (i=0 to 2)
UARTi receive register
D
D
D
D
D
D
5
4
3
2
1
D
D
D
D
D
D
5
4
3
2
1
UARTi transmit register
Error signal output
No reverse
disable
IOPOL
=0
TxD data
Error signal
reverse circuit
output circuit
IOPOL
Reverse
Error signal output
=1
enable
SP: Stop bit
PAR: Parity bit
UART2 receive
0
buffer register
Address 037E
16
Address 037F
16
UART2 transmit
0
buffer register
Address 037A
16
Address 037B
16
TxD2
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