Renesas M16C/29 Series Hardware Manual page 63

M16C/29 Group
Peripheral clock select register (Note)
b7 b6 b5 b4 b3 b2
0 0 0 0 0
Note: Write to this register after setting the PRC0 bit of PRCR register to "1" (write enable).
Processeor mode register 2 (Note 1)
b7 b6 b5 b4 b3 b2
0 0
Note 1: Write to this register after setting the PRC1 bit of PRCR register to "1" (write enable).
Note 2: This bit can only be rewritten while the PLC07 bit is "0" (PLL turned off). Also, to select a 16MHz or
higher PLL clock or sytem clock, set this bit to "0" (2 wait). Note that if the clock source for the CPU clock is
to be changed from the PLL clock to another, the PLC07 bit must be set to "0" before setting the PM20 bit.
Note 3: Once this bit is set to "1", it cannot be cleared to "0" in a program.
Note 4: Setting the PM21 bit to "1" results in the following conditions:
• The BCLK is not halted by executing the WAIT instruction.
• Writting to the following bits has no effect.
CM02 bit of CM0 register
CM05 bit of CM0 register (main clock is not halted)
CM07 bit of CM0 register (CPU clock source does not change)
CM10 bit of CM1 register (stop mode is not entered)
CM11 bit of CM1 register (CPU clock source does not change)
CM20 bit of CM2 register (oscillation stop, re-oscillation detection function settings do not change)
All bit of PLC0 register (PLL frequency synthesizer setting do not change)
Note 5: Setting the PM22 bit to "1" results in the following conditions:
• The on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the watchdog timer
count source.
• The CM10 bit of CM1 register is disabled against write. (Writing a "1" has no effect, nor is stop mode
entered.)
• The watchdog timer does not stop when in wait mode.
Note 6: For NMI function, the PM24 bit must be set to "1"(NMI function) in first instruction after rest. Once this bit is
set to "1", it cannot be cleared to "0" in a program. When the PM24 bit is set to "1", the P8
must be "0".
Note 7: SD input is valid regardless of the PM24 setting.
Figure 7.6. PCLKR Register and PM2 Register
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
Symbol
b1 b0
PCLKR
Bit name
Bit symbol
Timers A, B clock select bit
(Clock source for the timers
PCLK0 A, B, the timer S, the dead
timer, SI/O3, SI/O4 and
multi-master I
SI/O clock select bit
PCLK1 (Clock source for UART0
to UART2)
Reserved bit
(b4-b2)
Clock output function
PCLK5
expansion select bit
Reserved bit
(b7-b6)
Symbol
b1 b0
PM2
Bit name
Bit symbol
PM20 Specifying wait when
accessing SFR
System clock protective bit
PM21
WDT count source
PM22
protective bit
Reserved bit
(b3)
P8 /NMI configuration bit
PM24 5
Nothing is assigned. When write, set to
(b7-b5)
its content is indeterminate.
page 43 of 402
Address When reset
025E 00000011
16 2
Function
0 : f
2
1 : f
1
2 C bus)
0 : f
2SIO
1 : f
1SIO
"0"
Must set to
Refer to Table 7.5.3.1 Function
of CLKOUT pin
"0"
Must set to
Address When reset
001E XXX00000
16 2
Function
0 : 2 wait
1 : 1 wait
(Note 2)
0 : Clock is protected by PRCR
register
1 : Clock modification disabled
(Note 3,4)
0 : CPU clock is used for the
watchdog timer count source
1 : On-chip oscillator clock is used
for the watchdog timer count
(Note 3,5) source
Must set to "0"
0 : P8 function (NMI disable)
5
1 : NMI function
(Note 6,7)
"0"
7. Clock Generation Circuit
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
. When read,
direction register
5