Interrupt Level Mask Register (Ps: Ilm); Fig. 2.23 Configuration Of Interrupt Level Mask Register (Ilm); Table 2-5 Interrupt Level Mask Register (Ilm) And Interrupt Level (High/Low) - Fujitsu MB90420/5 (A) Series Hardware Manual

MB90420/5 (A) SERIES F

2.7.6 Interrupt Level Mask Register (PS: ILM)

The interrupt level mask register (ILM) is a 3-bit register to indicate the level of the interrupt accepted by the
CPU.
n Interrupt level mask register (ILM)
Figure 2.23 shows the configuration of the interrupt level mask register (ILM). For details of the interrupt,
see Chapter 6.
ILM
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
ILM2 ILM1 ILM0
PS

Fig. 2.23 Configuration of Interrupt Level Mask Register (ILM)

The interrupt level mask register (ILM) indicates the level of the interrupt that the CPU is currently accepting.
The value of this register is compared to the value of the IL0 to IL2 bits of the interrupt control register
(ICR00 to ICR15) that corresponds to the interrupt request of each resource. The CPU performs interrupt
processing only when the interrupt enable flag is set to enable (CCR: I = 1) and an interrupt request of a
smaller value than the value of these bits is issued.
• When the interrupt is accepted, its interrupt level value is set in the interrupt level mask register (ILM), and
subsequent interrupts of a level equal to or lower than that level are no longer accepted.
• All bits of the interrupt level mask register (ILM) are initialized to 0 by a reset. Consequently, the interrupt
level of this register is set to the highest, meaning that interrupts are disabled.
• The assembler instruction can use the 8-bit immediate value transfer instruction that is transferred to the
interrupt level mask register (ILM), but only the lower 3 bits of that data is actually used.

Table 2-5 Interrupt Level Mask Register (ILM) and Interrupt Level (high/low)

ILM2
0
0
0
0
1
1
1
1
2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
RP
bit 9
B4 B3 B2 B1
ILM1 ILM0
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
bit 8 bit 7 bit 6 bit 5
B0 — I S
Interrupt Level
0
1
2
3
4
5
6
7
2-24
CCR
bit 4 bit 43 bit 2 bit 1
T N Z V
Interrupt Level (high/low)
High (interrupts disabled)
Low
Initial value
bit 0
of ILM
000
C B