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MB90335 Series
13.2.1
PWC Control Status Register (PWCSR)
Configuration and function of PWC control status register (PWCSR) are described.
■ PWC Control Status Register (PWCSR)
Figure 13.2-2 shows the bit configuration of PWC control status register (PWCSR).
Figure 13.2-2 Bit Configuration of PWC Control Status Register (PWCSR)
00005D
00005C
R/W
: Readable/Writable
R
: Read only
The function of each bit in the PWC control status register (PWCSR) is described in the following.
[bit15, bit14] STRT, STOP (Timer Start Bit, Timer Stop Bit)
This bit controls to start, restart, and stop the 16-bit up count timer. Timer operation status is displayed
when reading.
The table below shows the function of STRT and STOP bit.
Table 13.2-1 Functions for Write Operation (Controlling the 16-bit Up Count Timer
STRT
0
0
1
1
*: Enable use for clear bit instruction.
CM44-10137-6E
bit
15
14
13
12
STRT STOP EDIR EDIE OVIR OVIE
H
(R/W) (R/W)
(R)
(R/W) (R/W) (R/W)
7
6
5
4
bit
H
CKS1 CKS0 PIS1
PIS0
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Operation)
STOP
0
1
0
1
FUJITSU MICROELECTRONICS LIMITED
11
10
9
8
ERR
Reserved
(R)
(R/W)
3
2
1
0
S/C
MOD2 MOD1 MOD0
Operation control functions
The influence is not in the function none/the operation.
Timer start/restart (count enabled).
Timer operation forced stop (count disabled).
The influence is not in the function none/the operation.
CHAPTER 13 PWC TIMER
13.2 Register of PWC Timer
PWCSR
PWC control status register
Initial value 0000000X
B
PWCSR
PWC control status register
Initial value 00000000
B
*
*
293
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