Control Status Register (Adcs2) - Fujitsu FR60 Hardware Manual

CHAPTER 12 A/D CONVERTER
12.2.2

Control Status Register (ADCS2)

The control status register (ADCS2) controls the A/D converter and indicates its status.
■ Bit Configuration of the Control Status Register (ADCS2)
The bit configuration of the control status register (ADCS2) is shown below.
Address : 000078
[Bits 15 to 12] ACS3 to ACS0 (analog channel set)
The ACS3 to ACS0 bits specify the channels that are to be targets of A/D conversion.
• In single conversion mode, these bits specify one channel as the target of conversion.
• In scan conversion mode, these bits specify the channel on which scanning is to start (see Section "12.3
Operation of the A/D Converter").
- If a channel from AN0 to AN3 is specified, the channels from the specified channel to AN3 are
scanned and converted.
- If a channel from AN4 to AN7 is specified, the channels from the specified channel to AN7 are
scanned and converted.
- If a channel from AN8 to AN11 is specified, the channels from the specified channel to AN11 are
scanned and converted.
• The register in which converted data is stored depends on the channel that is converted.
Note that the same data registers are used to store the data converted from three groups of channels
(AN0 to AN3, AN4 to AN7, and AN8 to AN11).
If, for example, channel AN4 or AN8 is converted after the AN0 channel has been converted, the data
converted from AN4 or AN8 is written over the stored data converted from AN0, corrupting the data
converted from AN0.
• The ACS3 to ACS0 bits must not be set to a value from 1100
written to these bits, the data set in data registers ADTH0 to ADTH3 is corrupted.
370
bit 15 14 13
ACS3 ACS2 ACS1
H
0 0 0
R/W R/W R/W
12 11 10 9
ACS0 - - CREG SCAN
0 - - 0
R/W - - R/W
8
ADCS2
<− Initial value
0
<− Bit attribute
R/W
to 1111 . If any of these values is
B B