Counter Control Register H1 (Ccrh1) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER

13.2.2 Counter control register H1 (CCRH1)

This section describes the configuration and explains the function of counter control
register H1 (CCRH1).
I Counter control register H1 (CCRH1)
The bit configuration of the counter control register H1 (CCRH1) is shown below.
Figure 13.2-3 Bit configuration of counter control register H1 (CCRH1)
Bit
CCRH1
Address: 000071
Counter control register H1 (CCRH1) consists of bits that have the functions explained below.
[Bit 14] CDCF (count direction reversal flag)
This bit is set when the count direction changes. It is set in the count start mode when the
count direction changes from up to down or from down to up.
Only writing "0" is permitted, and "1" cannot be written.
Read-modify-write type instructions return "1" irrespective of bit values.
CDCF
0
1
[Bit 13] CFIE (count direction reversal interrupt enable)
This bit is used to control interrupt output if CDCF is defined. It generates an interrupt in the
count start mode when the count direction changes.
CFIE
0
1
256
15 14 13 12
- CDCF CFIE CLKS CMS1 CMS0 CES1 CES0 -0000000
H
R/W R/W R/W R/W
Direction reversal detection
No direction reversals (initial value)
One or more reversals of direction
Direction reversal interrupt output
Direction reversal interrupt output prohibit (initial value)
Direction reversal interrupt output permit
11 10 9 8
R/W R/W R/W
Initial value
B