Table 3-3 Oscillation Stabilization Wait Time Based On Setting Of Clock Selection Register (Ckscr) - Fujitsu MB90420/5 (A) Series Hardware Manual

MB90420/5 (A) SERIES F
Vcc
CLK
CPU Operation
HCLK: Oscillation clock
Fig. 3.2 Oscillation Stabilization Wait Time of Evaluation Products/Flash and

Table 3-3 Oscillation Stabilization Wait Time Based on Setting of Clock Selection Register (CKSCR)

WS1 WS0
Indicated in Parentheses is Obtained when the Oscillation Clock Frequency is 4 MHz.
0 0
0 1
1 0
1 1
HCLK: Oscillation clock frequency
Note: The oscillator of ceramic or crystal requires an oscillation stabilization wait time, from the start of
oscillation until the stable oscillation, generally ranging from a few ms to dozens of ms. Set the
value appropriate for the oscillator being used. For details, see Section 4.1.
n Oscillation stabilization wait reset state
The power-on reset, stop mode or reset in the sub-clock mode is performed after the elapse of the oscillation
stabilization wait time generated by the time-base timer. At this point, if the external reset input is not
cancelled, the reset is performed after canceling the external reset.
2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
17 17
2 /HCLK 2 /HCLK
Voltage-lowering Oscillation
circuit stabilization stabilization wait
wait time time
Mask Products at Power-on Reset
The oscillation Stabilization Wait Time
10
2 /HCLK (about 0.256 ms)
13
2 /HCLK (about 2.048 ms)
15
2 /HCLK (about 8.192 ms)
18
2 /HCLK (about 65.536 ms)
3-6