Table of Contents
Advertisement
LW
2.1.15 Lower-Byte Write (
)
This signal is a combination of R/W low and LDS low for writing the lower-byte of a 16-bit
port. This signal simplifies memory system design by explicitly signalling that data is valid
on the lower portion of the data bus on a write operation. LW is also decoded for external
bus masters.
OE
2.1.16 Output Enable (
)
OE is a combination of R/ W high and an active data strobe (UDS or LDS ). OE is also
decoded for external bus masters.
RESET
2.1.17 Reset (
)
The external assertion of this bi-directional, open-drain signal can start a system
initialization sequence by resetting the processor. The processor assertion of RESET
(from executing a RESET instruction) resets all external devices of a system without
affecting the internal state of the processor. The interaction of internal and external
RESET , and the HALT signal is described in paragraph 3.5 Reset Operation.
2.2 CHIP SELECT SIGNALS
These eight three-state signals provide address decodes with programmable base and
range. CS7 –CS4 are only available in chip select mode (AMODE bit =1). CS3–CS0 are
always available.
2.3 DRAM CONTROLLER SIGNALS
The following signals are used to control an external DRAM for the MC68306.
CAS1
CAS0
2.3.1 Column Address Strobe (
–
)
These three-state signals provide column address strobe timing for external DRAM. CAS0
controls data lines D15–D8 and CAS1 controls D7–D0.
RAS1
RAS0
2.3.2 Row Address Strobe (
–
)
These three-state signals provide row address strobe timing for external DRAM. Each
RAS controls a separate bank of DRAM.
DRAMW
2.3.3 DRAM Write Signal (
)
This signal provides write control for external DRAM.
2.4 INTERRUPT CONTROL AND PARALLEL PORT SIGNALS
The following signals are used for interrupt control on the MC68306.
MOTOROLA
MC68306 USER'S MANUAL
2- 9
Advertisement
Table of Contents
