Memory Management Unit Instructions; Multiprocessor Instructions - Motorola MC68030 User Manual

3.2.10 Memory Management Unit Instructions

The PFLUSH instructions flush the address translation caches (ATCs) and can optionally
select only nonglobal entries for flushing. PTEST performs a search of the address
translation tables, storing results in the MMU status register and loading the entry into the
ATC. Table 3–10 summarizes these instructions.
Instruction Operand Syntax
PFLUSHA none
PFLUSHA.N none
PFLUSH (An)
PFLUSH.N (An)
PTEST (An)

3.2.11 Multiprocessor Instructions

The TAS, CAS, and CAS2 instructions coordinate the operations of processors in
multiprocessing systems. These instructions use read-modify-write bus cycles to ensure
uninterrupted updating of memory. Coprocessor instructions control the coprocessor
operations. Table 3–11 lists these instructions.
Table 3-11. Multiprocessor Operations (Read-Modify-Write)
Instruction Operand Syntax
CAS Dc,Du,〈ea〉
CAS2 Dc1:Dc2,Du1:Du2,(
Rn):(Rn)
TAS
〈label〉
cpBcc
cpDBcc label,Dn
cpGEN User Defined
cpRESTORE
cpSAVE
cpScc
cpTRAPcc
#〈data〉
MOTOROLA
Table 3-10. MMU Instructions
Operand Size
none
none
none
none
none
Operand Size
Read-Modify-Write
8, 16, 32
8, 16, 32
〈ea〉
8
Coprocessor
16, 32
16
User Defined
〈ea〉
none
〈ea〉
none
〈ea〉
8
none none
16, 32
MC68030 USER'S MANUAL
Invalidate all ATC entries
Invalidate all nonglobal ATC entries
Invalidate ATC entries at effective address
Invalidate nonglobal ATC entries at effective address
Information about logical address → MMU status register
destination — Dc → CC; if Z then Du → destination
else destination→Dc
dual operand CAS
destination — 0; set condition codes; 1 → destination [7]
if cpcc true, then PC + d → PC
if cpcc false then Dn –1 → Dn
if Dn ≠ –1, then PC + d → PC
operand → coprocessor
restore coprocessor state from 〈ea〉
save coprocessor state at 〈ea〉
if cpcc true, then 1's → destination; else 0's → destination
if cpc true, then TRAPcc exception
Instruction Set Summary
Operation
Operation
3-13