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The OEA defines encodings of mtspr and mfspr to provide access to supervisor-level
registers. The instructions are listed in Table 2-57.
Table 2-57. Move to/from Special-Purpose Register Instructions (OEA)
Name
Mnemonic
Syntax
Move to Special· Purpose Register
mtspr
SPR,rS
Move from Special-Purpose Register
mfspr
rO,SPR
Encodings for the architecture-defined SPRs are listed in Table 2-48. Encodings for
MPC750-specific, supervisor-level SPRs are listed in Table 2-49. Simplified mnemonics
are provided for mtspr and mfspr in Appendix F, "Simplified Mnemonics," in The
Programming Environments Manual. For a discussion of context synchronization
requirements when altering certain SPRs, refer to Appendix E, "Synchronization
Programming Examples," in The Programming Environments Manual.
2.3.6.3 Memory Control Instructions-OEA
Memory control instructions include the following:
• Cache management instructions (supervisor-level and user-level)
•
Segment register manipulation instructions
• Translation lookaside buffer management instructions
This section describes supervisor-level memory control instructions. Section 2.3.5.3,
"Memory Control Instructions-VEA," describes user-level memory control instructions.
2.3.6.3.1 Supervisor-Level Cache Management Instruction-(OEA)
Table 2-58 lists the only supervisor-level cache management instruction.
Table 2-58. Supervisor-Level Cache Management Instruction
Name
Mnemonic Syntax
Implementation Notes
Oata
dcbi
rA,rB
The EA is computed, translated, and checked for protection violations. For cache
Cache
hits, the cache block is marked I regardless of whether it was marked E or M. A
Block
dcbi is not broadcast unless HIOO[ABE)
=
1, regardless of WIMG settings. The
Invalidate
instruction acts like a store with respect to address translation and memory
protection. It executes regardless of whether the cache is disabled or locked.
The exception priorities (from highest to lowest) for dcbi are as follows:
1 BAT protection violation-OSI exception
2
TLB protection violation-OSI exception
See Section 2.3.5.3.1, "User-Level Cache Instructions-VEA," for cache instructions that
provide user-level programs the ability to manage the on-chip caches.
If
the effective
address references a direct-store segment, the instruction is treated as a no-op.
2-66
MPC750 RISC Microprocessor User's Manual
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