Effects Of Dynamic Bus Sizing And Operand Misalignment; Memory Alignment And Port Size Influence On Write Bus Cycles - Motorola MC68030 User Manual

Figures 7-15 and 7-16 show an example of a long-word transfer to an odd
address in long-ward-organized memory. In this example, a long-word access
is attempted beginning at the least significant byte of a long-ward-organized
memory. Only one byte can be transferred in the first bus cycle. The second
bus cycle then consists of a three-byte access to a long-word boundary. Since
the memory is long-word organized, no further bus cycles are necessary.
Figure 7-17 shows the equivalent operation for a cachable data read cycle.
7.2.3 Effects of Dynamic Bus Sizing and Operand Misalignment
The combination of operand size, operand alignment, and port size deter-
mines the number of bus cycles required to perform a particular memory
access. Table 7-6 shows the number of bus cycles required for different
operand sizes to different port sizes with all possible alignment conditions
for write cycles and noncachable read cycles.
Table 7-6. Memory Alignment and Port Size Influence
on Write Bus Cycles
A1/AO
Number of Bus Cycles
00 01 10 11
Instruction* 1 :2:4
N/A N/A N/A
Byte Operand 1: 1: 1 1:1:1 1: 1: 1 1: 1: 1
Word Operand 1:1 :2 1 :2:2 1:1 :2 2:2:2
Long-Word Operand 1 :2:4 2:3:4 2:2:4 2:3:4
Data Port Size - 32 Bits:16 Bits:8 Bits
*Instruction prefetches are always two words from a long-word boundary.
This table shows that bus cycle throughput is significantly affected by port
size and alignment. The MC68030 system designer and programmer should
be aware of and account for these effects, particularly in time-critical appli-
cations.
MOTOROLA MC68030 USER'S MANUAL
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