Figure 7-6 Repeated Illegal Instruction; Interrupt Latency - Motorola DSP56800 Manual

Interrupts and the Processing States
Interrupt Control Cycle 1
Interrupt Control Cycle 2
Fetch
Decode
Execute
Instruction Cycle Count
i = Interrupt
ii = Interrupt Instruction Word
II = Illegal Instruction
n = Normal Instruction Word
In DO loops, if the illegal instruction is in the loop address (LA) location and the instruction preceding it
(that is, at LA-1) is being interrupted, the loop counter (LC) will be decremented as if the loop had reached
the LA instruction. When the interrupt service ends and the instruction flow returns to the loop, the
instruction after the illegal instruction will be fetched (since it is the next sequential instruction in the
flow).
7.3.8

Interrupt Latency

Interrupt latency represents the time between when an interrupt request first appears and when the first
instruction in an interrupt service routine is actually executed. The interrupt can only take place on
instruction boundaries, and so the length of execution of an instruction affects interrupt latency.
There are some special cases to consider. The SWI, STOP, and WAIT instructions are not interruptible.
Likewise, the REP instruction and the instruction it repeats are not interruptible.
A REP instruction and the instruction that follows it are treated as a single two-word instruction, regardless
of how many times it repeats the second instruction of the pair. Instruction fetches are suspended and will
be reactivated only after the LC is decremented to one (see Figure 7-7). During the execution of n2 in
Figure 7-7, no interrupts will be serviced. When LC finally decrements to one, the fetches are re-initiated,
and pending interrupts can be serviced.
7-16
Illegal Instruction Interrupt
n1 n2 n3 n4 REP
n1 n2 n3 n4
n1 n2 n3
1 2 3 4 5 6
Figure 7-6. Repeated Illegal Instruction
DSP56800 Family Manual
Recognized as Pending
i
n6 n7 — —
REP II — —
n4 REP REP REP
7 8 9 10
i
— ii1 ii2 n8
— — ii1 ii2 n8
II — — ii1 ii2 n8
11 12 13 14 15 16
AA0070