Jtag Test Logic Block Diagram; Jtag Instructions - Motorola M68060 User Manual

213
TDI
31
1-BIT BYPASS
3
TRST
TMS
TCK
9.1.2 JTAG Instruction Shift Register
The MC68060 IEEE 1149.1 implementation uses a 4-bit instruction shift register without par-
ity. The shift register transfers its value to a parallel hold register and applies one of sixteen
possible instructions, seven of which are defined as public customer-usable instructions, on
the falling edge of TCK when the TAP state machine is in the update-IR state (the other nine
instructions are private instructions to support manufacturing test and can cause destructive
behavior if used without proper understanding). The instructions may be loaded into the shift
portion of the register by placing the serial data on the TDI signal prior to each rising edge
of TCK. The most significant bit of the instruction shift register is the bit closest to the TDI
signal and the least significant bit is the bit closest to the TDO pin.
The public customer-usable instructions that are supported are listed with their encodings in
Table 9-2.
MOTOROLA
IEEE 1149.1 Test (JTAG) and Debug Pipe Control Modes
214-BIT BOUNDARY SCAN REGISTER
32-BIT IDCODE REGISTER
0
INSTRUCTION APPLY & DECODE REGISTER
4-BIT INSTRUCTION SHIFT REGISTER
TAP CONTROLLER
Figure 9-1. JTAG Test Logic Block Diagram
M68060 USER'S MANUAL
0
0
0
M
TDO
U
X
9-3