Samsung S5PC110 Manual page 993

Risc microprocessor
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S5PC110_UM
7.4.10 COMMAND COMPLETE SEQUENCE
The sequence to complete the SD Command is shown in
following errors can occur during this sequence: Command Index/ End bit/ CRC/ Timeout Error.
Steps to complete the SD command:
1. Wait for the Command Complete Interrupt. If the Command Complete Interrupt occurs, go to step (2).
2. Write 1 to Command Complete (STACMDCMPLT) in the Normal Interrupt Status register to clear this bit.
3. Read the Response register and get necessary information in accordance with the issued command.
4. Judge whether the command uses the Transfer Complete Interrupt or not. If it uses Transfer Complete,
proceed with step (5). If not, go to step (7).
5. Wait for the Transfer Complete Interrupt. If the Transfer Complete Interrupt occurs, go to step (6).
6. Write 1 to Transfer Complete (STATRANCMPLT) in the Normal Interrupt Status register to clear this bit.
7. Check for errors in Response Data. If there is no error, proceed with step (8). If there is an error, go to
step (9).
8. Return Status of "No Error".
9. Return Status of "Response Contents Error".
NOTE:
1.
While waiting for the Transfer Complete interrupt, the Host Driver issues commands that do not use the busy signal.
2.
The Host Driver monitors Transfer Complete to judge the Auto CMD12 (Stop Command) complete.
3.
If the last block of un-protected area is read using memory multiple blocks read command (CMD18), OUT_OF_RANGE
error may occur even if the sequence is correct. The Host Driver must ignore this error. This error appears in the response
of Auto CMD12 or in the response of the next memory command.
,
,
Figure 7-7
Figure 7-8
7 SD/MMC CONTROLLER
and
Figure 7-9
Figure 7-10
. The
7-13

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