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FEATURES
Sound IF (SIF) processor
SIF demodulator and broadcast stereo decoder
NICAM (BG, DK, I, L), A2 (BG, DK, M), BTSC (M, N), EIAJ (M)
Automatic sound IF standard detection
Fully programmable 28-bit audio processor for enhanced
ATV sound—default TV audio flow loaded on reset
Implements Analog Devices and third-party branded audio
algorithms
Adjustable digital delay line for audio/video
Synchronization for up to 200 ms stereo delay
High performance 24-bit ADC and DAC
94 dB DNR performance on DAC channels
95 dB DNR performance on ADC channels
Dual headphone outputs with integrated amplifiers
High performance pulse-width modulation (PWM) digital
outputs
Multichannel digital baseband I/O
4 stereo synchronous digital I
One 6-channel sample rate converter (SRC) and one
stereo SRC supporting input sample rates from
5 kHz to 50 kHz
One stereo synchronous digital I
S/PDIF output with S/PDIF input mux capability
2
Fast I
C control
Operates from 3.3 V (analog), 1.8 V (digital core), and 3.3 V
(digital interface)
Available in 80-lead LQFP
APPLICATIONS
General-purpose consumer audio postprocessing
Home audio
DVD recorders
Home theater in a box (HTIB) systems and DVD receivers
Audio processing subsystems for DTV-ready TVs
Analog broadcast capability for iDTVs
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Audio Processor for Advanced TV with
Sound IF Demodulator and Stereo Decoder
2
S input channels
2
S output
PRODUCT OVERVIEW
The ADAV4622 is an enhanced audio processor targeting
advanced TV applications with full support for digital and
analog baseband audio as well as multistandard broadcast SIF
demodulation and decoding.
The audio processor, by default, loads a dedicated TV audio
flow that incorporates full matrix switching (any input to any
output), automatic volume control that compensates for volume
changes during advertisements or when switching channels,
dynamic bass, a multiband equalizer, and up to 200 ms of stereo
delay memory for audio-video synchronization.
Alternatively, Analog Devices, Inc., offers an award-winning
graphical programming tool (SigmaStudio™) that allows custom
flows to be quickly developed and evaluated. This allows the
creation of customer-specific audio flows, including use of the
Analog Devices library of third-party algorithms.
The analog I/O integrates Analog Devices proprietary
continuous-time, multibit Σ-Δ architecture to bring a higher
level of performance to ATV systems, required by third-party
algorithm providers to meet system branding certification. The
analog input is provided by 95 dB dynamic range (DNR) ADCs,
and analog output is provided by 94 dB DNR DACs.
The main speaker outputs can be supplied as a digitally
modulated PWM stream to support digital amplifiers.
The ADAV4622 includes multichannel digital inputs and
outputs. In addition, digital input channels can be routed
through integrated sample rate converters (SRC), which are
capable of supporting any arbitrary sample rate from 5 kHz
to 50 kHz.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
©2008–2009 Analog Devices, Inc. All rights reserved.
ADAV4622
www.analog.com
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Table of Contents
Related Manuals for Analog Devices ADAV4622
Summary of Contents for Analog Devices ADAV4622
- Page 1 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
- Page 2 ADAV4622 TABLE OF CONTENTS Features ....................1 VREF .................... 20 Applications ..................1 FILTA and FILTD ............... 20 Product Overview ................1 PWM1A, PWM1B, PWM2A, PWM2B, PWM3A, PWM3B, PWM4A, and PWM4B .............. 20 ...
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Page 3: Functional Block Diagram
HPOUT1L HPOUT1R SDIN0 SYNCHRONOUS SDIN1 MULTICHANNEL SDIN2 AUXOUT1L DIGITAL INPUTS SDIN3 AUXOUT1R AUXOUT2L AUXIN1L AUXIN1R AUXOUT2R HPOUT2L AUXIN2L HPOUT2R AUXIN2R SYNCHRONOUS DELAY AUXOUT3L MEMORY ADAV4622 AUXOUT3R Figure 1. ADAV4622 with PWM-Based Speaker Outputs Rev. B | Page 3 of 28... -
Page 4: Specifications
ADAV4622 SPECIFICATIONS AVDD = 3.3 V, DVDD = 1.8 V, ODVDD = 3.3 V, operating temperature = −40°C to +85°C, master clock = 24.576 MHz, measurement bandwidth = 20 Hz to 20 kHz, ADC input signal = DAC output signal = 1 kHz, unless otherwise noted. - Page 5 ADAV4622 Parameter Unit Test Conditions/Comments FM Output Level at 400% Deviation Mode 53.7 % FS A2 (DK, I, BG), Mono, V = 100 mV, f = 400 Hz, Δf = 200 kHz, rms detector 53.6 % FS BTSC (M, N), Mono, V...
- Page 6 ADAV4622 Parameter Unit Test Conditions/Comments A2 (M) PERFORMANCE Measured at analog audio output, video = 75% color bar, = 4.5 MHz, f = 4.724 MHz, f = 1 kHz, Δf = 25 kHz (100%), deemphasis = 75 μs, measuring BW = 20 Hz to...
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Page 7: Headphone Amplifier
ADAV4622 Parameter Unit Test Conditions/Comments ADC SECTION Number of Channels Two stereo channels Full-Scale Input Level μA rms Resolution Bits Dynamic Range (Stereo Channel) A-Weighted −60 dBFS with respect to full-scale analog input Total Harmonic Distortion + Noise (Stereo −90 −3 dBFS with respect to full-scale analog input... -
Page 8: Digital Input/Output
ADAV4622 Parameter Unit Test Conditions/Comments Number of Channels Two channels (SRC1), six channels (SRC2) Dynamic Range A-Weighted −60 dBFS input (worst-case input f = 50 kHz) Total Harmonic Distortion + Noise −113 −3 dBFS input (worst-case input f = 50 kHz) -
Page 9: Timing Specifications
ADAV4622 TIMING SPECIFICATIONS Table 2. Parameter Description Unit Comments MASTER CLOCK AND RESET MCLKI frequency 3.072 24.576 MCLKI MCLKI high MCLKI low RESET low RESET MASTER CLOCK OUTPUT Period jitter MCLK_OUT high MCLK_OUT low C PORT SCL clock frequency SCL high... -
Page 10: Timing Diagrams
ADAV4622 TIMING DIAGRAMS = 1/ MCLKI MCLKI RESET RESET Figure 2. Master Clock and Reset Timing DVDD Figure 3. Master Clock Output Timing LRCLK1 BCLK1 SDINx SDO0 Figure 4. Serial Port Slave Mode Timing LRCLK1 BCLK1 SDINx SDO0 Figure 5. Serial Port Master Mode Timing 100µA... - Page 11 ADAV4622 1.8V 1.65V DVDD 0.18V 1.0s MAX 3.3V 3.0V AVDD ODVDD 0.33V 1.0s MAX Figure 7. Power-Up Sequence Timing 1.8V 1.65V DVDD 0.18V 1.0s MAX 3.3V 3.0V AVDD ODVDD 0.33V 1.0s MAX Figure 8. Power-Down Sequence Timing Rev. B | Page 11 of 28...
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Page 12: Absolute Maximum Ratings
ADAV4622 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3. θ is specified for the worst-case conditions, that is, a device Parameter Rating soldered in a circuit board for surface-mount packages. DVDD to DGND 0 V to 2.2 V ODVDD to DGND 0 V to 4 V Table 4. -
Page 13: Pin Configuration And Function Descriptions
ADAV4622 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 FILTA HPOUT2L PIN 1 VREF AVDD AGND HPOUT1R AVDD HPOUT1L SIF_REFP AGND SIF_REFCM AGND... - Page 14 ADAV4622 Pin No. Mnemonic Description C Data. C Clock. SPDIF_IN5/LRCLK2 External Input to S/PDIF Mux/Left/Right Clock for SRC2 (Default). SPDIF_IN6/BCLK2 External Input to S/PDIF Mux/Bit Clock for SRC2 (Default). DGND Digital Ground. DVDD Digital Supply (1.8 V). SDIN0 Serial Data Input 0/SRC Data Input.
- Page 15 ADAV4622 Pin No. Mnemonic Description AVDD DAC Supply (3.3 V). AGND DAC Ground. AGND DAC Ground. AVDD DAC Supply (3.3 V). AUXOUT1L Left Auxiliary Output 1. AUXOUT1R Right Auxiliary Output 1. AUXOUT2L Left Auxiliary Output 2. AUXOUT2R Right Auxiliary Output 2.
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Page 16: Typical Performance Characteristics
ADAV4622 TYPICAL PERFORMANCE CHARACTERISTICS –30 –20 –60 –40 –90 –60 –120 –80 –150 –100 –180 –120 –210 –140 –240 –160 –270 –180 –300 FREQUENCY (kHz) FREQUENCY (kHz) Figure 10. DAC Composite Filter Response (48 kHz) Figure 13. ADC Composite Filter Response (48 kHz) –20... - Page 17 ADAV4622 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 –160 –160 4000 8000 12000 16000 20000 4000 8000 12000 16000 20000 FREQUENCY (Hz) FREQUENCY (Hz) Figure 19. ADC Total Harmonic Distortion + Noise Figure 16. DAC Dynamic Range –20...
- Page 18 In some regions, the transmitted signal can deviate from the attenuation. specification. In order for the ADAV4622 to decode these high deviation signals correctly, the appropriate modulation level Gain Error must be selected.
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Page 19: Pin Functions
SPDIF_IN (external) signals, the signal is MCLKI/XIN simply passed through from input to output. Master clock input. The ADAV4622 uses a PLL to generate the LRCLK0, BCLK0, LRCLK1, BCLK1, LRCLK2, AND appropriate internal clock for the audio processing core. A clock... - Page 20 Mute input request. This active-low input pin controls the Differential pulse-width modulation outputs are suitable for muting of the output ports (both analog and digital) from the driving Class-D amplifiers. ADAV4622. When low, it asserts mute on the outputs that are enabled in the audio flow. PWM_READY RESET This pin is set high when PWM is enabled and stable.
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Page 21: Functional Descriptions
Supported SIF Standards The ADAV4622 supports automatic standard detection, which is enabled by default. The ASD controller configures the SIF The ADAV4622 supports all worldwide standards, as shown in processor with the optimum register settings based on the Table 6. -
Page 22: Adc Inputs
MCLKI edges to determine the state of the pin (high or BCLK0 low). Because the pin has an internal pull-down resistor default, LRCLK1 BCLK1 the address of the ADAV4622 is 0x34 (write) and 0x35 (read). LRCLK2 An alternate address, 0x36 (write) and 0x37 (read), is available BCLK2 SDIN0 AUDIO by tying the SDO0 pin to ODVDD via a 10 kΩ... - Page 23 20 bits, or 24 bits. The default is 24 bits. Asynchronous Inputs S Mode The ADAV4622 has two SRCs, SRC1 and SRC2, that can be In I S mode, the data are left-justified, MSB first, with the MSB used for converting digital data, which is not synchronous to the master clock.
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Page 24: Pwm Outputs
Figure 28. Right-Justified Mode PWM OUTPUTS HEADPHONE OUTPUTS In the ADAV4622, the main outputs are available as four PWM There are two stereo headphone amplifier outputs capable output channels, which are suitable for driving Class-D amplifiers. of driving 32 Ω loads at 1 V rms. HPOUT1 is shared with... -
Page 25: Audio Processor
HARDWARE MUTE CONTROL processor and the system controller. The ADAV4622 mute input can be used to mute any of the Once a custom flow is created, a user-customized register map analog or digital outputs. When the MUTE pin goes low, the can be defined for controlling the flow. - Page 26 ADAV4622 LOADING A CUSTOM AUDIO PROCESSING FLOW ADDRESS The ADAV4622 can load a custom audio flow from an external AUDIO AUDIO C ROM. The boot process is initiated by a simple control PROCESSOR PROCESSOR MEMORY register write. The EEPROM device address and the EEPROM DATA start address for the audio flow ROMs can all be programmed.
- Page 27 ADAV4622 PWM1 (LHIGH) PWM2 (RHIGH) BEEPER PWM3 (LLOW) AUXIN1L PWM4 AUXIN1R (RLOW) AUXIN2L AUXIN2R SDIN0 CHANNEL TO INPUT SDIN1 MUXES HPOUT1L/ SDIN2/SRC2 AUXOUT4L CHANNEL B SDIN3/SRC2 CHANNEL C HPOUT1R/ AUXOUT4R SRC1 SRC2 AUXOUT2L/ CHANNEL A HPOUT2L AUXOUT2R/ HPOUT2R S/PDIF OUTL...
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Page 28: Outline Dimensions
220°C to 235°C. Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips.
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