Single-Wire Half-Duplex Communication; Figure 292. Usart Data Clock Timing Diagram (M=1); Figure 293. Rx Data Setup/Hold Time - ST STM32F446 Series Reference Manual

RM0390
Note: The function of SCLK is different in Smartcard mode. Refer to the Smartcard mode chapter
for more details.
25.4.10

Single-wire half-duplex communication

The single-wire half-duplex mode is selected by setting the HDSEL bit in the USART_CR3
register. In this mode, the following bits must be kept cleared:
•
LINEN and CLKEN bits in the USART_CR2 register,
•
SCEN and IREN bits in the USART_CR3 register.
The USART can be configured to follow a single-wire half-duplex protocol where the TX and
RX lines are internally connected. The selection between half- and full-duplex
communication is made with a control bit 'HALF DUPLEX SEL' (HDSEL in USART_CR3).
Universal synchronous asynchronous receiver transmitter (USART)

Figure 292. USART data clock timing diagram (M=1)

Figure 293. RX data setup/hold time

RM0390 Rev 4 825/1328
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