Inter-processor communication controller (IPCC)
9.4.9
IPCC register map
Register name
Offset
Reset value
IPCC_C1CR
0x0000
Reset value
IPCC_C1MR
0x0004
Reset value
IPCC_C1SCR
0x0008
Reset value
IPCC_C1TOC2SR
0x000C
Reset value
IPCC_C2CR
0x0010
Reset value
IPCC_C2MR
0x0014
Reset value
IPCC_C2SCR
0x0018
Reset value
IPCC_C2TOC1SR
0x001C
Reset value
Refer to
392/1461
Table 69. IPCC register map and reset values
Section 2.6 on page 70
0
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
for the register boundary addresses.
RM0453 Rev 1
RM0453
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
Need help?
Do you have a question about the STM32WL5 Series and is the answer not in the manual?
Questions and answers