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CHAPTER 17 DMA CONTROLLER
17.3.4 Register of the descriptor in RAM
This register stores information for each channel for DMA transfer.
This register has a size of 12 bytes per channel, and uses the memory space at the
address allocated by the DPDP.
For details on the start address of the descriptor for each channel, see Table 17.3-1
"Descriptor address for each channel".
I Descriptor start word
The register configuration of the descriptor start word is given below.
31
15
7
SCS1
R/W
Initial value: Undefined
[Bits 31 to 16] DMACT transfer count
Specify the number of times the DMA is to be transferred. With 0000
transferred 65536 times.
The value is decremented by one for each transfer.
[Bits 15 to 12] Empty
[Bits 11 to 8] BLK block size
Specify the size of a block to be transferred in single/block transfer mode.
If you specify 0, a block size of 16 is set. For single transfer, specify 1.
[Bits 7 and 6] SCS1 and SCS0 transfer source address update mode
[Bits 5 and 4] DCS1 and DCS0 transfer destination update mode
Specify the mode for updating the transfer source and destination addresses for each
transfer.
You can specify the combinations listed in the following table.
370
DMACT
R/W
14
13
12
6
5
4
SCS0
DCS1
DCS0
R/W
R/W
R/W
11
10
9
BLK
R/W
3
2
1
WS1
WS0
MOD1
R/W
R/W
R/W
16
8
0
MOD0
R/W
set, the DMA is
H
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