Block Diagrams - Renesas 9FGV100 Series User Manual

Block Diagrams

Figure 3. 9FGV1004 Block Diagram
Figure 4. 9FGV1002 Block Diagram
Figure 5. 9FGV1001 Block Diagram
Equations
F = F × Feedback Divider (see register 0x1F)
VCO CRYSTAL
9FGV1004: F = F
OUT3 VCO
F = F
OUT2 VCO
F = F
OUT0 OUT1
9FGV1002: F = F
OUT0 OUT1
9FGV1001: F = F
OUT0 OUT1
Limits
F : 10MHz ~ 40MHz
CRYSTAL
F : 2300MHz ~ 2600MHz
VCO
Integer Divider 1 and 2: 8 ~ 4095
FOD: 4 ~ 255
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/ Integer Divider 1 (see registers 0x20 and 0x22)
/ Integer Divider 2 (see registers 0x21 and 0x22)
= F × JA Multiplier / (2 × FOD) (see registers 0x10 ~ 0x18 and 0x24)
VCO
= F = F = F × JA Multiplier / (2 × FOD) (see registers 0x10 ~ 0x18 and 0x24)
OUT2 OUT3 VCO
= F = F = F / Integer Divider 1 (see registers 0x20 and 0x22)
OUT2 OUT3 VCO
9FGV100x Register Descriptions and Programming Guide User Guide
9 November 18, 2016