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3 Interval time
This section describes the interval time of the watchdog timer
The interval times of the watchdog timer are shown in Table 3-1. If the counter of watchdog
timer is not cleared, a watchdog reset is generated between the minimum time and the
maximum time.
Count clock type
Timebase timer output
(main clock = 4MHz)
Watch prescaler output
( sub-clock = 32.768KHz)
Sub-CR timer
(sub-CR clock = 50-200KHz)
*1: CS [1:0] = 00
, CSP = 1
B
The interval time varies depending on the timing of clearing the watchdog timer. Figure 3-1
shows the correlation between the timing of clearing the watchdog timer and the interval time
when the timebase timer output 2
(main clock = 4MHz).
Figure 3-1: Clearing Timing and Interval Time of Watchdog Timer
Please note that program must clear the counter of the watchdog timer within the minimum
time.
WATCHDOG TIMER V1.1
Chapter 3 Interval time
Count clock switch bit
CS[1:0], CSP
000
(SWWDT)
B
010
(SWWDT)
B
100
(SWWDT)
B
110
(SWWDT)
B
XX1
(SWWDT) or
B
1
HWWDT*
(read only)
B
Table 3-1: Interval Times of Watchdog Timer
21
/F
(F
: main clock) is selected as the count clock
CH
CH
MCU-AN-500013-E-11 – Page 8
Interval time
Minimum time
21
2
/F
524 ms
CH
20
2
/F
262 ms
CH
14
2
/F
500 ms
CL
13
2
/F
250 ms
CL
16
2
/F
328 ms
CRL
Maximum time
1.05 s
524 ms
1.00 s
500 ms
2.62 s
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