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Fujitsu MB90930 Series Hardware Manual

F2mc-16lx 16-bit microcontroller

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FUJITSU MICROELECTRONICS

CM44-10150-1E

CONTROLLER MANUAL

2

F

MC-16LX

16-BIT MICROCONTROLLER

MB90930 Series

HARDWARE MANUAL

Table of Contents

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Page 1 FUJITSU MICROELECTRONICS CM44-10150-1E CONTROLLER MANUAL MC-16LX 16-BIT MICROCONTROLLER MB90930 Series HARDWARE MANUAL...
Page 3 MC-16LX 16-BIT MICROCONTROLLER MB90930 Series HARDWARE MANUAL For the information for microcontroller supports, see the following web site. http://edevice.fujitsu.com/micom/en-support/ FUJITSU MICROELECTRONICS LIMITED...
Page 5 ■ Objectives and Intended Reader Thank you very much for your continued patronage of Fujitsu Microelectronics products. The MB90930 series has been developed as one of the general-purpose products of the F 16LX family, which is an original 16-bit single-chip microcontroller compatible with the Application Specific IC (ASIC).
Page 6 ■ Organization of this manual This manual consists of the following 27 chapters and 1 appendices: CHAPTER 1 OVERVIEW This chapter describes features and provides the basic specification of the MB90930 series. CHAPTER 2 CPU This chapter describes F2MC-16LX CPU. CHAPTER 3 INTERRUPT This chapter describes the relationships between interrupts and the extended intelligent I/O service (EI...
Page 7 CHAPTER 18 CAN CONTROLLER This chapter describes an overview of the CAN controller and its functions. CHAPTER 19 LCD CONTROLLER/DRIVER This chapter describes the functions and operations of the LCD controller/driver. CHAPTER 20 LOW-VOLTAGE/CPU OPERATION DETECTION RESET CIRCUIT This chapter describes the functions and operations of the low-voltage/CPU operation detection reset circuit.
Page 8 (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.
Page 9: Table Of Contents
CONTENTS CHAPTER 1 OVERVIEW ..................1 Overview of MB90930 Series ....................2 Features ..........................3 Block Diagram ........................5 Package Dimension ......................6 Pin Assignment ........................7 Pin Functions ........................8 I/O Circuit Types ........................ 17 Precautions for Handling Device ..................21 CHAPTER 2 CPU ....................
Page 10 3.6.3 Operation of the Extended intelligent I/O Service (EI OS) ........... 90 3.6.4 Extended Intelligent I/O Service (EI OS) Procedure ............ 92 3.6.5 Extended Intelligent I/O Service (EI OS) Processing Time .......... 93 Exception Handling Interrupt by Execution of Undefined Instruction ......... 95 Stack Operations of Interrupt Handling ................
Page 11 8.3.2 Description of Port 0 Operation .................. 182 Port 1 ..........................184 8.4.1 Port 1 Registers (PDR1, DDR1) ................. 186 8.4.2 Description of Port 1 Operation .................. 187 Port 2 ..........................189 8.5.1 Port 2 Data Register (PDR2, DDR2) ................191 8.5.2 Description of Port 2 Operation ..................
Page 12 9.4.1 Watchdog Timer Operation ..................268 9.4.2 Operation of Time-base Timer ..................270 9.4.3 Operation of Watch Timer ..................273 Notes on Using the Watchdog Timer/Time-base Timer ..........275 Program Example for Watchdog Timer/Time-base Timer ..........278 CHAPTER 10 INPUT CAPTURE ................. 281 10.1 Outline of Input Capture ....................
Page 13 13.2.1 Real-Time Watch Timer Control Register ..............357 13.2.2 Sub-Second Data Register ..................359 13.2.3 Second/Minute/Hour/Day Data Registers ..............360 13.3 Interrupts of Real-Time Watch Timer ................362 CHAPTER 14 DELAY INTERRUPT GENERATION MODULE ......363 14.1 Overview of Delay Interrupt Generation Module ............. 364 14.2 Operation of Delay Interrupt Generation Module .............
Page 14 17.4.4 Reception Data Register and Transmission Data Register (RDR/TDR) ....443 17.4.5 Extended Status Control Register (ESCR) ..............445 17.4.6 Extended Communication Control Register (ECCR) ..........447 17.4.7 Baud Rate Generator Registers 0 and 1 (BGRn0/BGRn1) ........449 17.5 Interrupts of LIN-UART ....................450 17.5.1 Timing of Reception Interrupt Generation and Flag Set ..........
Page 15 18.6 Using CAN Controller ...................... 540 18.7 Procedure of Transmission via Message Buffer (x) ............541 18.8 Procedure of Reception Via Message Buffer (x) ............. 543 18.9 Specifying the Multi-level Message Buffer Configuration ..........545 18.10 CAN WAKE UP Function ....................547 18.11 Precautions When Using CAN Controller ................
Page 16 22.2.4 Decrement Grade Register(SGDR0/SGDR1) ............617 22.2.5 Tone Count Register(SGTR0/SGTR1) ............... 618 CHAPTER 23 ROM MIRROR FUNCTION SELECT MODULE ......619 23.1 Outline of the ROM Mirror Function Select Module ............620 23.2 ROM Mirror Function Select Register (ROMM) ............... 621 CHAPTER 24 1M-BIT FLASH MEMORY ............
Page 17 Execution Cycle Count ....................720 Effective address field ..................... 723 How to Read the Instruction List ..................724 MC-16LX Instruction List ..................... 727 Instruction Map ........................ 741 INDEX ........................763 xiii...
Page 19 Main changes in this edition. Page Changes (For details, refer to main body.) First edition...
Page 21: Chapter 1 Overview
CHAPTER 1 OVERVIEW This chapter describes features and provides the basic specification of the MB90930 series. 1.1 Overview of MB90930 Series 1.2 Features 1.3 Block Diagram 1.4 Package Dimension 1.5 Pin Assignment 1.6 Pin Functions 1.7 I/O Circuit Types 1.8 Precautions for Handling Device...
Page 22: Overview Of Mb90930 Series
1.1 Overview of MB90930 Series MB90930 Series Overview of MB90930 Series This section outlines MB90930 series products. ■ Overview of MB90930 Series Table 1.1-1 gives an outline of MB90930 series products. Table 1.1-1 Outline of MB90930 Series Products MB90V930- MB90V930- Features...
Page 23: Features
Features This section describes the features of MB90930 series. ■ Features Table 1.2-1 shows the features of MB90930 series. Table 1.2-1 Features of MB90930 Series (1 / 2) Function Features 16-bit reload timer Allows 16-bit reload timer operations (e.g. toggle output and one shot output (4 channels) selectable) and the selection of the event count function.
Page 24 CHAPTER 1 OVERVIEW 1.2 Features MB90930 Series Table 1.2-1 Features of MB90930 Series (2 / 2) Function Features 8-bit PWM signal is mixed with tone frequency from 8-bit reload counter. Sound generator PWM frequency: 125kHz, 62.5kHz, 31.2kHz, 15.6kHz (when fcp = 32 MHz)
Page 25: Block Diagram
CHAPTER 1 OVERVIEW 1.3 Block Diagram MB90930 Series Block Diagram This section shows a block diagram of MB90930 series products. ■ Block Diagram Figure 1.3-1 shows a block diagram of MB90930 series products. Figure 1.3-1 Block Diagram of MB90930 Series...
Page 26: Package Dimension
CHAPTER 1 OVERVIEW 1.4 Package Dimension MB90930 Series Package Dimension This section shows a package dimension of MB90930 series products. ■ Package Dimension Figure 1.4-1 shows a package dimension. Figure 1.4-1 Package Dimension 120-pin plastic LQFP Lead pitch 0.50 mm Package width ×...
Page 27: Pin Assignment
CHAPTER 1 OVERVIEW 1.5 Pin Assignment MB90930 Series Pin Assignment This section shows the pin assignment of MB90930 series products. ■ Pin Assignment Figure 1.5-1 shows the pin assignment. Figure 1.5-1 Pin Assignment P30/SEG06 P31/SEG07 P32/SEG08 P33/SEG09 P34/SEG10 DVSS P35/SEG11...
Page 28: Pin Functions
CHAPTER 1 OVERVIEW 1.6 Pin Functions MB90930 Series Pin Functions This section describes the pin functions of MB90930 series products. ■ Description of Pin Functions Table 1.6-1 describes the pin functions. Table 1.6-1 Pin Functions (1 / 9) I/O Circuit Pin no.
Page 29 CHAPTER 1 OVERVIEW 1.6 Pin Functions MB90930 Series Table 1.6-1 Pin Functions (2 / 9) I/O Circuit Pin no. Pin name Description type * General-purpose I/O port. TOT0 16-bit reload timer ch.0 TOT output pin. PPG3 16-bit PPG ch.3 output pin.
Page 30 CHAPTER 1 OVERVIEW 1.6 Pin Functions MB90930 Series Table 1.6-1 Pin Functions (3 / 9) I/O Circuit Pin no. Pin name Description type * General-purpose I/O port. SEG07 LCD controller/driver segment output pin. General-purpose I/O port. SEG08 LCD controller/driver segment output pin.
Page 31 CHAPTER 1 OVERVIEW 1.6 Pin Functions MB90930 Series Table 1.6-1 Pin Functions (4 / 9) I/O Circuit Pin no. Pin name Description type * General-purpose I/O port. SEG20 LCD controller/driver segment output pin. General-purpose I/O port. SEG21 LCD controller/driver segment output pin.
Page 32 CHAPTER 1 OVERVIEW 1.6 Pin Functions MB90930 Series Table 1.6-1 Pin Functions (5 / 9) I/O Circuit Pin no. Pin name Description type * General-purpose I/O port. A/D converter input pin. General-purpose I/O port. A/D converter input pin. General-purpose I/O port.
Page 33 CHAPTER 1 OVERVIEW 1.6 Pin Functions MB90930 Series Table 1.6-1 Pin Functions (6 / 9) I/O Circuit Pin no. Pin name Description type * General-purpose output-only port. PWM2M1 Stepping motor controller ch.1 output pin. AN15 A/D converter input pin. General-purpose output-only port.
Page 34 CHAPTER 1 OVERVIEW 1.6 Pin Functions MB90930 Series Table 1.6-1 Pin Functions (7 / 9) I/O Circuit Description Pin no. Pin name type * General-purpose I/O port. LCD controller/driver reference power supply pin. General-purpose I/O port. LCD controller/driver reference power supply pin.
Page 35 CHAPTER 1 OVERVIEW 1.6 Pin Functions MB90930 Series Table 1.6-1 Pin Functions (8 / 9) I/O Circuit Pin no. Pin name Description type * General-purpose I/O port. SIN2 UART ch.2 serial data input pin. General-purpose I/O port. SOT2 UART ch.2 serial data output pin.
Page 36 CHAPTER 1 OVERVIEW 1.6 Pin Functions MB90930 Series Table 1.6-1 Pin Functions (9 / 9) I/O Circuit Pin no. Pin name Description type * External capacitor pin. Connect an 0.1 μF capacitor between this pin and VSS. 15,105 Power supply input pins.
Page 37: I/O Circuit Types
CHAPTER 1 OVERVIEW 1.7 I/O Circuit Types MB90930 Series I/O Circuit Types This section describes the types of the input/output circuits for each pin. ■ I/O Circuit Types Table 1.7-1 shows the types of input/output circuits for each pin. Table 1.7-1 I/O Circuit Types (1 / 4)
Page 38 CHAPTER 1 OVERVIEW 1.7 I/O Circuit Types MB90930 Series Table 1.7-1 I/O Circuit Types (2 / 4) Type Circuit Remarks Input-only pin • CMOS hysteresis input CMOS hysteresis input =0.8Vcc / 0.2Vcc) Note: The MD2 pin of the Flash memory products uses this circuit type.
Page 39 CHAPTER 1 OVERVIEW 1.7 I/O Circuit Types MB90930 Series Table 1.7-1 I/O Circuit Types (3 / 4) Type Circuit Remarks A/D converter input/general-purpose port P-ch Pout • CMOS output (I = ±4 mA) • CMOS hysteresis input N-ch Nout =0.8Vcc / 0.2Vcc) •...
Page 40 CHAPTER 1 OVERVIEW 1.7 I/O Circuit Types MB90930 Series Table 1.7-1 I/O Circuit Types (4 / 4) Type Circuit Remarks High current output port and high Pout P-ch current (SMC pin) High current • CMOS output N-ch Nout = ±30 mA) •...
Page 41: Precautions For Handling Device
Do not apply a voltage higher than VCC or lower than VSS to input pins and output pins of MB90930 series products. Moreover, do not apply a voltage exceeding the rating range between VCC and VSS. When a voltage exceeding the rating is applied, a latch-up may occur.
Page 42 CHAPTER 1 OVERVIEW 1.8 Precautions for Handling Device MB90930 Series ■ Processing of A/D Converter Power Supply Pins If not used, the A/D converter must be connected so that AVCC= VCC and AVSS=AVRH= VSS. ■ Use of External Clock When an external clock is used, oscillation stabilization wait time shall be applied at recovery from power-on reset, sub clock mode and stop mode.
Page 43 Apply a voltage to the power supply for high-current output buffer pin (DVCC/DVSS) even when the high-current output buffer pin is used as a general-purpose port. ■ Pull-up/Pull-down Resistor The MB90930 series supports neither internal pull-up nor pull-down resistors. Use external components if necessary. ■ Precautions when Sub Clock Mode is not Used If no oscillator is connected to the X0A and X1A pins, apply pull-down processing to the X0A pin and leave the X1A pin open.
Page 44 MB90930 Series ■ Precautions for PLL Clock Mode Operation If the PLL clock mode is selected on MB90930 series, it may attempt to be working with the free-run frequency of self-oscillating circuit in the PLL when the resonator is disconnected or clock input is stopped.
Page 45: Chapter 2 Cpu
This chapter describes F MC-16LX CPU. 2.1 Outline of CPU 2.2 Memory Space 2.3 Memory Map 2.4 Addressing 2.5 Allocation of Multiple-Byte Data in the Memory 2.6 Registers 2.7 Dedicated Registers 2.8 General-purpose Register 2.9 Prefix Codes CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 46: Outline Of Cpu
CHAPTER 2 CPU 2.1 Outline of CPU MB90930 Series Outline of CPU The F MC-16LX CPU core is a 16-bit CPU designed for applications in which high speed real-time processing is required, such as for various consumer devices and in vehicles. The F...
Page 47 CHAPTER 2 CPU 2.1 Outline of CPU MB90930 Series Note: MB90930 series uses only single-chip mode, accessing only memory space of built-in ROM, built-in RAM and built-in circuits for peripherals. CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 48: Memory Space
CHAPTER 2 CPU 2.2 Memory Space MB90930 Series Memory Space MC-16LX CPU has a memory space of 16 MB. The F MC-16LX CPU controls general-purpose data, program data and I/O data, all of which are allocated within the 16 MB memory space. A part of the memory space is used for special applications, such as for extended intelligent I/O service (EI descriptors, general-purpose registers and vector tables.
Page 49 CHAPTER 2 CPU 2.2 Memory Space MB90930 Series ■ ROM Area ● Vector table area (Address: FFFC00 to FFFFFF • Used as vector tables for vector call instructions, interrupt vectors and reset vectors. • Assigned to the highest portion of ROM area for setting the start address of the corresponding routine to address data in the applicable vector table.
Page 50: Memory Map
2.3 Memory Map MB90930 Series Memory Map This section describes the memory map for the different types of MB90930 series products. ■ Memory Map Figure 2.3-1 shows the memory map of MB90930 series. Figure 2.3-1 Memory Map MB90V930-102/ MB90F931/MB90F931S MB90V930-101 MB90931/MB90931S...
Page 51 CHAPTER 2 CPU 2.3 Memory Map MB90930 Series Notes: • If "no RO M mir ror f unction" is sele cted, see "C HAPTER 23 ROM MIRROR FUNCTION SELECT MODULE". • The upp er 00 ban k allows re ferencing RO M d ata in th e FF ban k as an imag e f or effectively using the C c ompiler's small mo del.
Page 52: Addressing
CHAPTER 2 CPU 2.4 Addressing MB90930 Series Addressing Both linear and bank address generation schemes are available. The linear scheme is used to directly specify all 24-bit addresses within the instruction. The bank scheme is used to specify upper 8-bit addresses via the bank register depending on how the data will be used and to specify the lower 16-bit addresses with instructions.
Page 53: Addressing With Linear Scheme
CHAPTER 2 CPU 2.4 Addressing MB90930 Series 2.4.1 Addressing with Linear Scheme There are two types of linear addressing: Directly addressing 24-bit addresses with an operand, and using the lower 24 bits of 32-bit general-purpose registers as address. ■ Specification with 24-bit Operand Figure 2.4-2 Example of Linear Addressing (Specification with 24-bit Operand)
Page 54: Addressing With Bank Scheme
CHAPTER 2 CPU 2.4 Addressing MB90930 Series 2.4.2 Addressing with Bank Scheme When applying the bank scheme, the 16 MB memory space is divided into 256 banks of 64 K bytes each, and the bank address corresponding to each space is specified via a bank register.
Page 55 CHAPTER 2 CPU 2.4 Addressing MB90930 Series Figure 2.4-4 shows the relationship between the memory space divided into banks and each register. Refer to Section "2.7.6 Bank Registers (PCB, DTB, USB, SSB, ADB)" for details. Figure 2.4-4 Physical Address of Each Bank Register...
Page 56: Allocation Of Multiple-Byte Data In The Memory
CHAPTER 2 CPU 2.5 Allocation of Multiple-Byte Data in the Memory MB90930 Series Allocation of Multiple-Byte Data in the Memory Multiple-byte data is written to memory, starting from the lower address in sequence. For 32-bit data, first the lower 16 bits are transferred, then the upper 16 bits.If a reset signal is input immediately after writing the lower part of the...
Page 57 CHAPTER 2 CPU 2.5 Allocation of Multiple-Byte Data in the Memory MB90930 Series ■ Allocating Multi-byte Data on the Stack Figure 2.5-3 shows the allocation of multiple-byte data on the stack. Figure 2.5-3 Allocating Multi-byte Data on the Stack PUSHW RW1,RW3...
Page 58: Registers
CHAPTER 2 CPU 2.6 Registers MB90930 Series Registers The F MC-16LX registers mostly has two types: CPU-internal dedicated registers, and general-purpose registers in the built-in RAM. ■ Dedicated Registers and General-purpose Registers Dedicated registers consist of dedicated hardware in the CPU and their use is limited by the CPU architecture.
Page 59: Dedicated Registers
CHAPTER 2 CPU 2.7 Dedicated Registers MB90930 Series Dedicated Registers The CPU contains the following 11 types of dedicated registers: • Accumulator (A) • User stack pointer (USP) • System stack pointer (SSP) • Processor status (PS) • Program counter (PC) •...
Page 60 CHAPTER 2 CPU 2.7 Dedicated Registers MB90930 Series Table 2.7-1 Initial Values of Dedicated Registers Dedicated register Initial value Accumulator (A) Undefined User stack pointer (USP) Undefined System stack pointer (SSP) Undefined bit15 to bit13 bit12 bit8 bit7 bit0 Processor status (PS)
Page 61: Accumulator (A)
CHAPTER 2 CPU 2.7 Dedicated Registers MB90930 Series 2.7.1 Accumulator (A) The accumulator (A) consists of two 16-bit registers (AH and AL) to temporarily store operation results or other data items. The A register is used as a 32-/16-/8-bit register, for the purpose of executing a variety of operations between memory and other registers, or between AH and AL registers.
Page 62 CHAPTER 2 CPU 2.7 Dedicated Registers MB90930 Series ● Byte-based arithmetic operations of the accumulator When executing a byte-based arithmetic operation instruction for the AL register, the upper 8 bits of the AL register before the operation are ignored, and the upper 8 bits of the operation result are all set to "0".
Page 63 CHAPTER 2 CPU 2.7 Dedicated Registers MB90930 Series Figure 2.7-6 Example of Accumulator (A) Transfers Between AL and AH (16-bit, Register Indirect) (Instruction to read long-word data from the address calculated as MOVW A,@RW1+6 RW1 content + 8-bit offset, then writing the result to the A register)
Page 64: Stack Pointers (Usp, Ssp)
CHAPTER 2 CPU 2.7 Dedicated Registers MB90930 Series 2.7.2 Stack Pointers (USP, SSP) There are two types of stack pointers: a user stack pointer (USP) and a system stack pointer (SSP). These are registers used to indicate the destination address in memory for data relocation or recovery when executing the PUSH instruction, POP instruction, or subroutines.
Page 65 CHAPTER 2 CPU 2.7 Dedicated Registers MB90930 Series Figure 2.7-7 shows an example of stack operations when the system stack is used. Figure 2.7-7 Stack Operation Instructions and Stack Pointers PUSHW A if the S flag is set to "0"...
Page 66: Processor Status (Ps)
CHAPTER 2 CPU 2.7 Dedicated Registers MB90930 Series 2.7.3 Processor Status (PS) The processor status register (PS) consists of CPU control bits and a variety of bits indicating the CPU state. ■ Bit Configuration of Processor Status (PS) The PS register consists of three registers listed below.
Page 67 CHAPTER 2 CPU 2.7 Dedicated Registers MB90930 Series ■ Condition Code Register (PS:CCR) This register consists of 8 bits including bits to represent operation result and the contents of data transfers as well as the bits to control the acceptance of interrupt requests.
Page 68 CHAPTER 2 CPU 2.7 Dedicated Registers MB90930 Series ● Carry flag (C) Set to "1" if, when an operation is executed, either carry-up from the highest bit or carry-down to the highest bit occurs. Otherwise, cleared to "0". ■ Register Bank Pointer (PS:RP) Used to indicate the start address in the general-purpose register bank currently used.
Page 69 CHAPTER 2 CPU 2.7 Dedicated Registers MB90930 Series ■ Interrupt Level Mask Register (PS:ILM) The interrupt level mask register (ILM) is a 3-bit register used to indicate the interrupt level the CPU can accept. Figure 2.7-12 shows the bit configuration of the interrupt level mask register (ILM). For the details of the interrupt, see "CHAPTER 3 INTERRUPTS".
Page 70: Program Counter (Pc)
CHAPTER 2 CPU 2.7 Dedicated Registers MB90930 Series 2.7.4 Program Counter (PC) The program counter (PC) is a 16-bit counter that indicates the lower 16-bits of the address in memory at which the instruction code that the CPU will execute next is stored.
Page 71: Direct Page Register (Dpr)
CHAPTER 2 CPU 2.7 Dedicated Registers MB90930 Series 2.7.5 Direct Page Register (DPR) The direct page register (DPR) is an 8-bit register used to specify bits 8 to 15 (addr8 to addr15) at the operand address when an instruction applying the abbreviated direct addressing scheme is executed.
Page 72: Bank Registers (Pcb, Dtb, Usb, Ssb, Adb)
". The PCB can be read but not written. Reading and writing is allowed for all bank registers other than the PCB. Note: The MB90930 series supports only the device built-in memory space. For information about the operations of each register, see Section "2.4.2 Addressing with Bank Scheme".
Page 73: General-Purpose Register
CHAPTER 2 CPU 2.8 General-purpose Register MB90930 Series General-purpose Register The general-purpose register is a memory block located in RAM at the , where 16 bits × 8 are allocated per bank. It may addresses 000180 to 00037F be used as either general-purpose 8-bit register (byte register R0 to R7), 16-bit register (word register RW0 to RW7) or 32-bit register (long word register RL0 to RL3).
Page 74 CHAPTER 2 CPU 2.8 General-purpose Register MB90930 Series Note: The register bank pointer (RP) is initialized to "00 " after a reset. ■ Register Bank The register bank consists of general-purpose registers (byte register R0 to R7, word register RW0 to RW7, long word register RL0 to RL3) used for a variety of operations and as pointers.
Page 75: Prefix Codes
MB90930 Series Prefix Codes Placing a prefix code before an instruction changes some of the operations. The MB90930 series has three types of prefix codes: • Bank Select Prefix (PCB, DTB, ADB, SPB) • Common Register Bank Prefix (CMR) • Flag Change Suppress Prefix (NCC) ■...
Page 76 CHAPTER 2 CPU 2.9 Prefix Codes MB90930 Series Table 2.9-2 Instructions Not Affected by Bank Select Prefix Instruction type Instruction Effect of bank select prefix MOVS MOVSW The bank register specified by the operand is String instruction SCEQ SCWEQ used irrespective of whether a prefix is...
Page 77 CHAPTER 2 CPU 2.9 Prefix Codes MB90930 Series Table 2.9-4 Instructions Requiring Caution When Common Register Bank Prefix (CMR) is Used Instruction type Instruction Description MOVS MOVSW String instruction SCEQ SCWEQ Do not add the CMR prefix to string instructions.
Page 78 CHAPTER 2 CPU 2.9 Prefix Codes MB90930 Series ■ Restrictions on Prefix Codes The three restrictions listed below are applied when using prefix codes. • No interrupt/hold request is accepted when a prefix code or an interrupt/hold suppress instruction is used.
Page 79 CHAPTER 2 CPU 2.9 Prefix Codes MB90930 Series ● Delayed effect of prefix codes If, as shown in Figure 2.9-2, a prefix code is placed before an interrupt/hold suppress instruction, the prefix code becomes effective with the first instruction after the interrupt/hold suppress instruction is issued.
Page 80 CHAPTER 2 CPU 2.9 Prefix Codes MB90930 Series FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 81: Chapter 3 Interrupt
3.3 Interrupt Control Registers and Peripheral Functions 3.4 Hardware Interrupt 3.5 Software Interrupt 3.6 Interrupt by Extended Intelligent I/O Service (EI 3.7 Exception Handling Interrupt by Execution of Undefined Instruction 3.8 Stack Operations of Interrupt Handling 3.9 Example Program for Interrupt Handling CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 82: Outline Of Interrupts
CHAPTER 3 INTERRUPT 3.1 Outline of Interrupts MB90930 Series Outline of Interrupts MC-16LX has 4 types of interrupt functions to interrupt the processing currently being performed and transferring the control to a separately defined program if an event occurs. • Hardware interrupt •...
Page 83 CHAPTER 3 INTERRUPT 3.1 Outline of Interrupts MB90930 Series ■ Interrupt Operation MC-16LX has 4 types of interrupt functions for starting and returning processing, as shown in Figure 3.1-1. Figure 3.1-1 Overall Operational Flow of Interrupt Processing START Main program...
Page 84: Interrupt Sources And Interrupt Vectors
CHAPTER 3 INTERRUPT 3.2 Interrupt Sources and Interrupt Vectors MB90930 Series Interrupt Sources and Interrupt Vectors MC-16LX has functions corresponding to 256 types of interrupt sources. There are 256 interrupt vector tables allocated starting with the highest address in memory. The interrupt vectors are shared by all interrupts.
Page 85 CHAPTER 3 INTERRUPT 3.2 Interrupt Sources and Interrupt Vectors MB90930 Series ■ Interrupt Sources and Interrupt Vectors/Interrupt Control Registers Table 3.2-2 shows the relationship between interrupt sources and the interrupt vectors/interrupt control registers except for software interrupts. Table 3.2-2 Interrupt Sources and Interrupt Vectors/Interrupt Control Registers...
Page 86: Interrupt Control Registers And Peripheral Functions
CHAPTER 3 INTERRUPT 3.3 Interrupt Control Registers and Peripheral Functions MB90930 Series Interrupt Control Registers and Peripheral Functions Interrupt control registers (ICR00 to ICR15) are located in the interrupt controller corresponding to all the peripheral functions that include interrupt functions. These registers control the interrupt and extended intelligent I/O service (EI OS).
Page 87: Interrupt Control Registers (Icr00 To Icr15)
CHAPTER 3 INTERRUPT 3.3 Interrupt Control Registers and Peripheral Functions MB90930 Series 3.3.1 Interrupt Control Registers (ICR00 to ICR15) The interrupt control registers correspond to all of the peripheral functions that use interrupt functions and control processing at interrupt request generation.
Page 88 CHAPTER 3 INTERRUPT 3.3 Interrupt Control Registers and Peripheral Functions MB90930 Series Figure 3.3-2 Interrupt Control Registers (ICR00 to ICR15) during Read Operations Read Operation Initial value Address 0000B0 − − --000111 0000BF Interrupt level setting bits Interrupt level 0 (highest)
Page 89: Functions Of Interrupt Control Registers
CHAPTER 3 INTERRUPT 3.3 Interrupt Control Registers and Peripheral Functions MB90930 Series 3.3.2 Functions of Interrupt Control Registers The interrupt control registers (ICR00 to ICR15) consist of bits with the following 4 functions: • Interrupt level setting bits (IL2 to IL0) •...
Page 90 CHAPTER 3 INTERRUPT 3.3 Interrupt Control Registers and Peripheral Functions MB90930 Series ■ Functions of Interrupt Control Registers ● Interrupt level setting bits (IL2 to IL0) These bits specify the interrupt level of the corresponding peripheral function. The interrupt level is initialized to level 7 (no interrupt) at reset.
Page 91 CHAPTER 3 INTERRUPT 3.3 Interrupt Control Registers and Peripheral Functions MB90930 Series ● Extended intelligent I/O service (EI OS) status bits (S1, S0) These bits are read-only bits. Their value is checked at the end of EI OS operation to determine the operational status (in operation or ended).
Page 92: Hardware Interrupt
CHAPTER 3 INTERRUPT 3.4 Hardware Interrupt MB90930 Series Hardware Interrupt Hardware interrupts are used to temporarily stop the execution of program that is being executed by the CPU in response to an interrupt request signal from a peripheral function and then transfer control to a user-defined interrupt handling program.
Page 93 CHAPTER 3 INTERRUPT 3.4 Hardware Interrupt MB90930 Series ■ Structure of Hardware Interrupt The hardware interrupt unit exists in the four separate sections, as shown in Table 3.4-1. To use hardware interrupts, these four sections must be set using the program.
Page 94 CHAPTER 3 INTERRUPT 3.4 Hardware Interrupt MB90930 Series ● Suppressing hardware interrupts by interrupt suppress instructions The 10 types of hardware interrupt suppress instructions shown in Table 3.4-2 will suppress detection of hardware interrupt requests and ignore any such interrupt request. Even if a valid hardware interrupt request is issued when these instructions are being executed, interrupt handling is not executed until another type of instruction is executed.
Page 95: Hardware Interrupt Operation
CHAPTER 3 INTERRUPT 3.4 Hardware Interrupt MB90930 Series 3.4.1 Hardware Interrupt Operation This section describes the operation from generation of a hardware interrupt request to the completion of interrupt handling. ■ Starting Hardware Interrupt ● Operation of peripheral function (generating an interrupt request) A peripheral function that uses hardware interrupt requests has an "interrupt request flag"...
Page 96 CHAPTER 3 INTERRUPT 3.4 Hardware Interrupt MB90930 Series ■ Hardware Interrupt Operation Figure 3.4-2 shows the operation from the generation of a hardware interrupt to the completion of interrupt handling. Figure 3.4-2 Hardware Interrupt Operation Internal data bus ⋅ ⋅...
Page 97: Operation Flow Of Hardware Interrupt
CHAPTER 3 INTERRUPT 3.4 Hardware Interrupt MB90930 Series 3.4.2 Operation Flow of Hardware Interrupt If an interrupt request is generated from a peripheral function, the interrupt controller transfers the respective interrupt level to the CPU. If the CPU state allows the acceptance of interrupts, the instruction currently being executed is...
Page 98: Procedure For Using Hardware Interrupt
CHAPTER 3 INTERRUPT 3.4 Hardware Interrupt MB90930 Series 3.4.3 Procedure for Using Hardware Interrupt To use an hardware interrupt, the system stack area, peripheral function, and interrupt control register (ICR) must be specified in advance. ■ Procedure for Using Hardware Interrupt An example procedure for using hardware interrupts is shown in Figure 3.4-4.
Page 99: Multiple Interrupts
CHAPTER 3 INTERRUPT 3.4 Hardware Interrupt MB90930 Series 3.4.4 Multiple Interrupts For hardware interrupts, multiple interrupts are enabled by setting different interrupt levels to a interrupt level setting bit (IL0, IL1, IL2) in the interrupt control register (ICR) for multiple interrupt requests from the peripheral function.
Page 100 CHAPTER 3 INTERRUPT 3.4 Hardware Interrupt MB90930 Series ■ Example of Multiple Interrupts In the following example for processing multiple interrupts, the timer interrupt has priority over A/D converter interrupts: the interrupt level of the A/D converter is set to 2, and the timer interrupt level is set to 1.
Page 101: Hardware Interrupt Processing Time
CHAPTER 3 INTERRUPT 3.4 Hardware Interrupt MB90930 Series 3.4.5 Hardware Interrupt Processing Time The duration between the generation of a hardware interrupt request and the execution of the interrupt handling routine must include the time until the instruction currently being executed is completed plus the interrupt handling time.
Page 102: Software Interrupt
CHAPTER 3 INTERRUPT 3.5 Software Interrupt MB90930 Series Software Interrupt Software interrupts have the function to transfer control from the program currently executed by the CPU to the interrupt handling program defined by the user when a software interrupt instruction (INT instruction) is executed.
Page 103 CHAPTER 3 INTERRUPT 3.5 Software Interrupt MB90930 Series ■ Software Interrupt Operation Figure 3.5-1 shows the operation performed from software interrupt generation to completion of interrupt handling. Figure 3.5-1 Software Interrupt Operation Internal data bus PS,PC… (2) Microcode Queue Fetch...
Page 104: Interrupt By Extended Intelligent I/O Service (Ei 2 Os)
CHAPTER 3 INTERRUPT 3.6 Interrupt by Extended Intelligent I/O Service (EI MB90930 Series Interrupt by Extended Intelligent I/O Service (EI The extended intelligent I/O service (EI OS) is a function to automatically transfer data between the peripheral function (I/O) and memory, and generates a hardware interrupt when the data transfer is completed.
Page 105 CHAPTER 3 INTERRUPT 3.6 Interrupt by Extended Intelligent I/O Service (EI MB90930 Series ■ Operation of Extended Intelligent I/O Service (EI Figure 3.6-1 shows the EI OS operation. Figure 3.6-1 Operation of Extended Intelligent I/O Service (EI Memory space Peripheral...
Page 106: Extended Intelligent I/O Service (Ei 2 Os) Descriptor (Isd)
CHAPTER 3 INTERRUPT 3.6 Interrupt by Extended Intelligent I/O Service (EI MB90930 Series 3.6.1 Extended Intelligent I/O Service (EI OS) Descriptor (ISD) The extended intelligent I/O service (EI OS) descriptor (ISD) is located in the internal RAM at the addresses "000100 "...
Page 107: Extended Intelligent I/O Service (Ei 2 Os) Descriptor (Isd) Registers
CHAPTER 3 INTERRUPT 3.6 Interrupt by Extended Intelligent I/O Service (EI MB90930 Series 3.6.2 Extended Intelligent I/O Service (EI OS) Descriptor (ISD) Registers The extended intelligent I/O service (EI OS) descriptor (ISD) consists of the registers listed below. • Data counter (DCT) •...
Page 108 CHAPTER 3 INTERRUPT 3.6 Interrupt by Extended Intelligent I/O Service (EI MB90930 Series ■ Extended Intelligent I/O Service (EI OS) Status Register (ISCS) The extended intelligent I/O service (EI OS) status register (ISCS) consists of 8 bits indicating whether buffer address pointer and I/O register address pointer can be updated or are fixed.
Page 109 CHAPTER 3 INTERRUPT 3.6 Interrupt by Extended Intelligent I/O Service (EI MB90930 Series ■ Buffer Address Pointer (BAP) The buffer address pointer (BAP) is a register consisting of 24 bits. It is used to store the address for the next EI OS data transfer.
Page 110: Operation Of The Extended Intelligent I/O Service (Ei 2 Os)
CHAPTER 3 INTERRUPT 3.6 Interrupt by Extended Intelligent I/O Service (EI MB90930 Series 3.6.3 Operation of the Extended intelligent I/O Service If a peripheral function issues an interrupt request and the corresponding interrupt control register (ICR) is set to start EI...
Page 111 CHAPTER 3 INTERRUPT 3.6 Interrupt by Extended Intelligent I/O Service (EI MB90930 Series Figure 3.6-7 Operation Flow of Extended Intelligent I/O Service (EI Interrupt request generated from peripheral function ISE = 1 Read ISD/ISCS Interrupt sequence Completion request from peripheral...
Page 112: Extended Intelligent I/O Service (Ei 2 Os) Procedure
CHAPTER 3 INTERRUPT 3.6 Interrupt by Extended Intelligent I/O Service (EI MB90930 Series 3.6.4 Extended Intelligent I/O Service (EI OS) Procedure The extended intelligent I/O service (EI OS) needs to set the system stack area, extended intelligent I/O service (EI OS) descriptor, peripheral function, interrupt control register (ICR) and others.
Page 113: Extended Intelligent I/O Service (Ei 2 Os) Processing Time
CHAPTER 3 INTERRUPT 3.6 Interrupt by Extended Intelligent I/O Service (EI MB90930 Series 3.6.5 Extended Intelligent I/O Service (EI Processing Time The time required for processing the extended intelligent I/O service (EI varies depending on the following factors: • Setting of EI OS status register (ISCS) •...
Page 114 CHAPTER 3 INTERRUPT 3.6 Interrupt by Extended Intelligent I/O Service (EI MB90930 Series ● When the data counter (DCT) stops counting (after the final data transfer is completed) When data transfer by EI OS is completed, the interrupt handling time is added to the total processing time, since a hardware interrupt is generated.
Page 115: Exception Handling Interrupt By Execution Of Undefined Instruction
CHAPTER 3 INTERRUPT 3.7 Exception Handling Interrupt by Execution of Undefined MB90930 Series Instruction Exception Handling Interrupt by Execution of Undefined Instruction MC-16LX handles exception handling by undefined instructions. Exception handling is basically performed in the same way as interrupt handling, i.e., the normal flow of processing is interrupted for starting exception handling if an exception event is detected at the instruction boundary.
Page 116: Stack Operations Of Interrupt Handling
CHAPTER 3 INTERRUPT 3.8 Stack Operations of Interrupt Handling MB90930 Series Stack Operations of Interrupt Handling If an interrupt is accepted, the content of the dedicated register is automatically saved to the system stack before processing branches to interrupt handling.
Page 117 CHAPTER 3 INTERRUPT 3.8 Stack Operations of Interrupt Handling MB90930 Series ■ Stack Area ● Allocation of the stack area The stack area is used for saving/returning the program counter (PC) as required for executing subroutine call instructions (CALL) and vector call instructions (CALLV) in addition to interrupt handling.
Page 118: Example Program For Interrupt Handling
CHAPTER 3 INTERRUPT 3.9 Example Program for Interrupt Handling MB90930 Series Example Program for Interrupt Handling An example program for interrupt handling is shown below. ■ Example Program for Interrupt Handling This is an example of an interrupt handling program that uses the external interrupt 0 (INT0) instruction.
Page 119 CHAPTER 3 INTERRUPT 3.9 Example Program for Interrupt Handling MB90930 Series LOOP ; Unconditional jump ;----------Interrupt program----------------------------------- ED_INT1: I:EIRR, #00H ; Prohibit acceptance of new ; INT0 RETI ; Return from interrupt CODE ENDS ;----------Vector setting-------------------------------------- VECT CSEG ABS=0FFH 0FFBCH ;...
Page 120 CHAPTER 3 INTERRUPT 3.9 Example Program for Interrupt Handling MB90930 Series ■ Specification of Processing for Sample Program of Extended Intelligent I/O Service (EI 1) If "H" level is detected for the signal input to the INT0 pin, the extended intelligent I/O service (EI OS) will start.
Page 121 CHAPTER 3 INTERRUPT 3.9 Example Program for Interrupt Handling MB90930 Series MOVW SP, A ; In this case, SSP is set, ; because the ; S-flag is set to "1". I:DDR5, #00000000B ; Set the P50/INT0 pin to "input" BAPL, #00H ;...
Page 122 CHAPTER 3 INTERRUPT 3.9 Example Program for Interrupt Handling MB90930 Series .ORG 0FFFFBCH ; Set vector to interrupt #16(10 .DATA.E WARI .ORG 0FFFFDCH ; Reset vector setting .DATA.E START .DATA.B ; Mode data setting START FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 123: Chapter 4 Reset
This chapter describes the reset operation. 4.1 Outline of Reset 4.2 Reset Sources and Oscillation Stabilization Wait Time 4.3 External Reset Pin 4.4 Reset Operation 4.5 Reset Source Bit 4.6 State of Each Pin by Reset CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 124: Outline Of Reset
CHAPTER 4 RESET 4.1 Outline of Reset MB90930 Series Outline of Reset If a reset source occurs, the CPU immediately suspends the processing currently being executed and enters the reset clear wait state. After the reset is cleared, processing starts at the address indicated by the reset vector.
Page 125 CHAPTER 4 RESET 4.1 Outline of Reset MB90930 Series ● External reset External reset is a reset that occurs when "L" level is input to the external reset pin (RST pin). The required time period for "L" level input to RST pin is 16 machine cycles (16/φ) or more.
Page 126 CHAPTER 4 RESET 4.1 Outline of Reset MB90930 Series Note: If a re set is ge nerated in s top m ode, ( 2 /HCLK (about 16.39 ms when using an os cillator of HCLK=4MHz) is used as the oscillation stabilization wait time.
Page 127: Reset Sources And Oscillation Stabilization Wait Time
4.2 Reset Sources and Oscillation Stabilization Wait Time MB90930 Series Reset Sources and Oscillation Stabilization Wait Time The MB90930 series has 6 types of reset sources. The oscillation stabilization wait time at reset depends on the reset source. ■ Reset Sources and Oscillation Stabilization Wait Time Table 4.2-1 shows the reset sources and oscillation stabilization wait time.
Page 128 CHAPTER 4 RESET 4.2 Reset Sources and Oscillation Stabilization Wait Time MB90930 Series Table 4.2-2 Oscillation Stabilization Wait Time Depending on Clock Selection Register (CKSCR) Settings Oscillation stabilization wait time ( ): for an oscillation clock frequency of 4MHz /HCLK (approx. 8.19ms) /HCLK (approx.
Page 129: External Reset Pin
External Reset Pin The external reset pin (RST pin) is a reset-input dedicated pin which generates an internal reset if "L" level is input. The MB90930 series starts reset operations in synchronization with CPU operation clock, however, only resets through external pins are performed asynchronously.
Page 130: Reset Operation
CHAPTER 4 RESET 4.4 Reset Operation MB90930 Series Reset Operation If a reset is released, the target for reading mode data and the reset vector is selected based on the setting of the mode pins, and a mode fetch is performed.
Page 131 CHAPTER 4 RESET 4.4 Reset Operation MB90930 Series Figure 4.4-2 Transfer of Reset Vector and Mode Data MC-16LX CPU core Memory space Mode register FFFFDF Mode data Micro ROM FFFFDE Reset vector bits 23 to 16 Reset sequence FFFFDD Reset vector bits 15 to 8...
Page 132: Reset Source Bit
CHAPTER 4 RESET 4.5 Reset Source Bit MB90930 Series Reset Source Bit The source for reset generation can be identified by reading the watchdog timer control register (WDTC) and the low-voltage/CPU operation detection reset control register (LVRC). ■ Reset Source Bit Each reset source has the corresponding flip flop as shown in Figure 4.5-1.
Page 133 CHAPTER 4 RESET 4.5 Reset Source Bit MB90930 Series ■ Correspondence between Reset Source Bit and Reset Source The configuration of reset source bits in the watchdog timer control register (WDTC) is shown in Figure 4.5-2, and the correspondence between the contents of reset source bits and reset sources is shown in Table 4.5-1.
Page 134 CHAPTER 4 RESET 4.5 Reset Source Bit MB90930 Series ■ State of Reset Source Bits Figure 4.5-3 State of Reset Source Bits State of flag Bit clearing State of flag at low-voltage Bit clearing State of flag at low-voltage at power-on detection (4.0V)
Page 135 CHAPTER 4 RESET 4.5 Reset Source Bit MB90930 Series ■ Notes on the Reset Source Bit ● When multiple reset sources occur When multiple reset sources occur, the corresponding reset source bits in the watchdog timer control register (WDTC) are set to "1". For example, if an external reset request from the RST pin and overflow of the watchdog timer occur at the same time, the ERST and WRST bits are both set to "1".
Page 136: State Of Each Pin By Reset
CHAPTER 4 RESET 4.6 State of Each Pin by Reset MB90930 Series State of Each Pin by Reset This section describes the state of each pin by reset. ■ State of Pins During Reset The state of a pin during reset is determined by the setting of the mode pins (MD2 to MD0=011 For the state of each pin during reset, see Section "6.7 Pin State in the Standby Mode and at...
Page 137: Chapter 5 Clock
5.1 Clock 5.2 Block Diagram of the Clock Generation Block 5.3 Clock Selection Register (CKSCR) 5.4 PLL/Sub clock Control Register (PSCCR) 5.5 Clock Mode 5.6 Oscillation Stabilization Wait Time 5.7 Connection of Oscillator and External Clock CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 138: Clock
CHAPTER 5 CLOCK 5.1 Clock MB90930 Series Clock The clock generation block controls the operation of the internal clock that controls operation of the CPU and peripheral functions. The clock generated by the clock generation block is called the machine clock. One cycle of machine clock is called one machine cycle.
Page 139 CHAPTER 5 CLOCK 5.1 Clock MB90930 Series Note: When the oper ating voltage is 5V , an oscillation cloc k of 3 MH z to 16 MHz can be generated. The maximum operating frequency for the CPU and peripheral functions is 32 MHz.
Page 140 CHAPTER 5 CLOCK 5.1 Clock MB90930 Series ■ Clock Supply Map Machine clock generated in the clock generation block is supplied as the operating clock for the CPU and peripheral functions. The operation of CPU and peripheral functions are affected by switching (clock mode) between a main clock and sub clock/ PLL clock and by a change in the PLL clock multiplication rate.
Page 141: Block Diagram Of The Clock Generation Block
CHAPTER 5 CLOCK 5.2 Block Diagram of the Clock Generation Block MB90930 Series Block Diagram of the Clock Generation Block The clock generation block consists of the following blocks: • Oscillation clock generation circuit • PLL multiplier circuit • Clock selector •...
Page 142 CHAPTER 5 CLOCK 5.2 Block Diagram of the Clock Generation Block MB90930 Series ● Oscillation clock generation circuit The oscillation clock (HCLK) is generated with connecting the oscillator to high speed oscillation pins (X0 and X1). ● Sub clock generation circuit The sub clock (SCLK) is generated either with connecting the low speed oscillator to oscillation pins (X0A and X1A) or with inputting an external clock.
Page 143: Register In The Clock Generation Block
CHAPTER 5 CLOCK 5.2 Block Diagram of the Clock Generation Block MB90930 Series 5.2.1 Register in the Clock Generation Block This section explains the register in the clock generation block. ■ List of the Registers in the Clock Generation Block and Its Initial Values Figure 5.2-2 lists the clock selection register and its initial values.
Page 144: Clock Selection Register (Ckscr)
CHAPTER 5 CLOCK 5.3 Clock Selection Register (CKSCR) MB90930 Series Clock Selection Register (CKSCR) The clock selection register (CKSCR) switches the main clock, sub clock, and PLL clock, and selects an oscillation stabilization wait time and PLL clock multiplication rate.
Page 145 CHAPTER 5 CLOCK 5.3 Clock Selection Register (CKSCR) MB90930 Series Table 5.3-1 Functions of Clock Selection Register (CKSCR) (1 / 3) Bit name Function Indicates whether the main clock or sub clock is selected as the machine clock. • When the sub clock operation flag bit (CKSCR: SCM) is "0" and the sub clock SCM: selection bit (CKSCR: SCS) is "1", it indicates that the clock is in the transition...
Page 146 CHAPTER 5 CLOCK 5.3 Clock Selection Register (CKSCR) MB90930 Series Table 5.3-1 Functions of Clock Selection Register (CKSCR) (2 / 3) Bit name Function Specifies whether to select the main clock or sub clock as the machine clock. • When the machine clock is switched from the main clock to the sub clock (CKSCR: SCS=1→0), it is synchronized with the sub clock and changed to...
Page 147 CHAPTER 5 CLOCK 5.3 Clock Selection Register (CKSCR) MB90930 Series Table 5.3-1 Functions of Clock Selection Register (CKSCR) (3 / 3) Bit name Function • These bits and CS2 bit in the PLL/sub clock control register (PSCCR) select a multiplication rate for the PLL clock.
Page 148: Pll/Sub Clock Control Register (Psccr)
CHAPTER 5 CLOCK 5.4 PLL/Sub clock Control Register (PSCCR) MB90930 Series PLL/Sub clock Control Register (PSCCR) The PLL/sub clock control register selects the PLL multiplication rate and the division ratio of the sub clock. This register is write-only. The value read from all bits is"1".
Page 149 CHAPTER 5 CLOCK 5.4 PLL/Sub clock Control Register (PSCCR) MB90930 Series Table 5.4-1 Function Description of Each Bit in the PLL/Sub Clock Control Register (PSCCR) Bit name Function bit15 These bits are not used. Undefined • Writing to these bits has no effect.
Page 150: Clock Mode
CHAPTER 5 CLOCK 5.5 Clock Mode MB90930 Series Clock Mode There are main clock mode and PLL clock mode. ■ Clock Mode ● Main clock mode The main clock mode uses the divided-by-two clock (oscillation clock), generated either by connecting the oscillator to oscillation pins (X0 and X1), as the operating clock for the CPU and peripheral functions.
Page 151 CHAPTER 5 CLOCK 5.5 Clock Mode MB90930 Series ● Transition from sub clock mode to main clock mode When the sub clock selection bit (CKSCR: SCS) is rewritten from "0" to "1", after the main clock oscillation stabilization wait time is elapsed, the transition from sub clock mode to main clock mode is made.
Page 152 CHAPTER 5 CLOCK 5.5 Clock Mode MB90930 Series Figure 5.5-1 shows a diagram of the state transition with machine clock switching. Figure 5.5-1 Diagram for State Transition with Machine Clock Selection Main --> Sub MCS = 1 MCM = 1...
Page 153 CHAPTER 5 CLOCK 5.5 Clock Mode MB90930 Series Write "0" to MCS bit End of PLL clock oscillation stabilization wait time & CS1, CS0= 00 & CS2= 0 End of PLL clock oscillation stabilization wait time & CS1, CS0= 01 &...
Page 154: Oscillation Stabilization Wait Time
CHAPTER 5 CLOCK 5.6 Oscillation Stabilization Wait Time MB90930 Series Oscillation Stabilization Wait Time When the power is turned on or when the stop mode is released where the oscillation clock is stopped, the oscillation clock requires some time to be stabilized (oscillation stabilization wait time) after the oscillation is started.
Page 155: Connection Of Oscillator And External Clock
MB90930 Series Connection of Oscillator and External Clock The MB90930 series contains a system clock generation circuit. An internal clock is generated with connecting the oscillator to the oscillation pin. A clock externally input to the low-speed oscillation pin can be used as the oscillation clock.
Page 156 CHAPTER 5 CLOCK 5.7 Connection of Oscillator and External Clock MB90930 Series FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 157: Chapter 6 Low-Power Consumption Mode
6.3 Low-power Consumption Mode Control Register (LPMCR) 6.4 CPU Intermittent Operation Mode 6.5 Standby Mode 6.6 State Transition Diagram 6.7 Pin State in the Standby Mode and at the Time of Reset 6.8 Notes on Using the Low-power Consumption Mode CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 158: Overview Of The Low-Power Consumption Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.1 Overview of the Low-power Consumption Mode MB90930 Series Overview of the Low-power Consumption Mode This series has the following CPU operating modes based on the operating clock selection and clock operation control. • Clock modes (PLL clock mode, main clock mode, sub clock mode) •...
Page 159 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.1 Overview of the Low-power Consumption Mode MB90930 Series ■ Clock Mode ● PLL clock mode In this mode the PLL multiplier clock of the oscillation clock (HCLK) is to operate the CPU and peripheral functions.
Page 160 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.1 Overview of the Low-power Consumption Mode MB90930 Series ■ Standby Mode In this mode, the power dissipation is reduced with stopping to provide the clock to the CPU (sleep mode), stopping to provide the clock to the CPU and peripheral functions (time-base timer mode) using a low-power consumption control circuit, or stopping the oscillation clock (stop mode).
Page 161: Block Diagram Of Low-Power Consumption Circuit
CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.2 Block Diagram of Low-power Consumption Circuit MB90930 Series Block Diagram of Low-power Consumption Circuit The low-power consumption control circuit consists of the following seven blocks: • CPU intermittent operation selector • Standby control circuit •...
Page 162 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.2 Block Diagram of Low-power Consumption Circuit MB90930 Series ● CPU intermittent operation selector Selects the number of clocks for pauses in the CPU intermittent operation mode. ● Standby control circuit Controls the CPU clock control circuit and peripheral clock control circuit, and makes transition to and cancellation of the low-power consumption mode.
Page 163: Low-Power Consumption Mode Control Register (Lpmcr)
CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.3 Low-power Consumption Mode Control Register (LPMCR) MB90930 Series Low-power Consumption Mode Control Register (LPMCR) The low-power consumption mode control register (LPMCR) makes the transition to and cancellation of the low-power consumption mode and configures the pause cycle count of the CPU clocks in the CPU intermittent operation mode.
Page 164 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.3 Low-power Consumption Mode Control Register (LPMCR) MB90930 Series Table 6.3-1 Functions of Low-power Consumption Mode Control Register (LPMCR) Bit name Function • Directs the transition to the stop mode. • When this bit is set to "1", the transition to the stop mode is made.
Page 165 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.3 Low-power Consumption Mode Control Register (LPMCR) MB90930 Series ■ Access to the Low-power Consumption Mode Control Register The transition to the low-power consumption mode (stop mode, sleep mode time-base timer mode or watch mode) is executed with writing to the low-power consumption mode control register.
Page 166: Cpu Intermittent Operation Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.4 CPU Intermittent Operation Mode MB90930 Series CPU Intermittent Operation Mode The CPU intermittent operation mode is used to reduce power dissipation with intermittent operation of the CPU while external buses or peripheral functions are operated with high-speed.
Page 167: Standby Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5 Standby Mode MB90930 Series Standby Mode The standby mode includes the sleep mode (PLL sleep mode, main sleep mode, sub sleep mode) and watch mode, stop mode. ■ Operation States in the Standby Mode Table 6.5-1 shows the operation states in the standby mode.
Page 168 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5 Standby Mode MB90930 Series Note: To set a pin to high impedance when the pin shares a port with peripheral functions in the stop mod e, watch mod e or t ime-base timer mode, disab le th e output of peripheral functions, and then set the STP bit to "1"...
Page 169: Sleep Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5 Standby Mode MB90930 Series 6.5.1 Sleep Mode When the transition to the sleep mode is directed in the lowpower consumption mode control register (LPMCR), if the PLL clock mode is set, the transition to...
Page 170 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5 Standby Mode MB90930 Series ■ Releasing Sleep Mode The low-power consumption control circuit cancels the sleep mode with a reset input or generation of an interrupt. ● Return by reset The mode is initialized to the main clock mode by reset.
Page 171 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5 Standby Mode MB90930 Series Figure 6.5-2 shows the cancellation of the sleep mode (external reset). Figure 6.5-2 Cancellation of Sleep Mode (External Reset) RST pin Sleep mode Main clock Oscillating PLL clock Oscillating CPU clock...
Page 172: Time-Base Timer Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5 Standby Mode MB90930 Series 6.5.2 Time-base Timer Mode In the time-base timer mode, the other functions than the source oscillation, time-base timer and watch timer are stopped. Therefore, all the functions except the time-base timer and the watch timer are stopped.
Page 173 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5 Standby Mode MB90930 Series ■ Releasing Time-base Timer Mode The low-power consumption control circuit releases the time-base timer mode with reset input or interrupt generation. ● Return by reset The mode is initialized to the main clock mode by reset.
Page 174: Watch Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5 Standby Mode MB90930 Series 6.5.3 Watch Mode In the watch mode, operations other than the sub clock and watch timer are stopped. Almost all the functions of the chip are stopped. This mode can be used with the dual clock product.
Page 175 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5 Standby Mode MB90930 Series ■ Releasing Watch Mode The low-power consumption control circuit cancels the watch mode with a reset input or generation of an interrupt. ● Return by reset When the watch mode is released by a reset source, after the watch mode is released, the system enters oscillation stabilization wait reset state.
Page 176: Stop Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5 Standby Mode MB90930 Series 6.5.4 Stop Mode In this mode, the source oscillation is stopped to stop all the functions. Therefore, data can be retained with the lowest-power dissipation. ■ Transition to Stop Mode When the STP bit in the low-power consumption mode control register (LPMCR) is set to "1",...
Page 177 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5 Standby Mode MB90930 Series ■ Releasing Stop Mode The low-power consumption control circuit cancels the stop mode with a reset input or generation of an interrupt. When the CPU returns from the stop mode and the oscillation clock (HCLK) and the sub clock (SCLK) are stopped.
Page 178 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5 Standby Mode MB90930 Series Figure 6.5-5 shows the cancellation of the stop mode (external reset). Figure 6.5-5 Cancellation of Stop Mode (External Reset) RST pin Stop mode Main clock Oscillating Oscillation stabilization wait PLL clock...
Page 179: State Transition Diagram
CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.6 State Transition Diagram MB90930 Series State Transition Diagram Figure 6.6-1 shows the transition diagram and conditions of the operation status. ■ State Transition Diagram Figure 6.6-1 State Transition Diagram CPU operation detetion reset Software reset...
Page 180 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.6 State Transition Diagram MB90930 Series ■ Operation States in the Low-power Consumption Mode Table 6.6-1 shows the operation states in the low-power consumption mode. Table 6.6-1 Operation States in the Low-power Consumption Mode Main...
Page 181: Pin State In The Standby Mode And At The Time Of Reset
CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.7 Pin State in the Standby Mode and at the Time of Reset MB90930 Series Pin State in the Standby Mode and at the Time of Reset This section describes pin states in the standby mode and at the time of reset, for each memory access mode.
Page 182 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.7 Pin State in the Standby Mode and at the Time of Reset MB90930 Series Note: To set a pin to high impedance when the pin shares a port with peripheral functions in the stop mod e, watch mod e or t ime-base timer mode, disab le th e output of peripheral functions, and then set the STP bit to "1"...
Page 183: Notes On Using The Low-Power Consumption Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.8 Notes on Using the Low-power Consumption Mode MB90930 Series Notes on Using the Low-power Consumption Mode Take notice of the following points when using the low-power consumption mode. • Transition to the standby mode and interrupts •...
Page 184 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.8 Notes on Using the Low-power Consumption Mode MB90930 Series ■ At Releasing the Stop Mode Before the transition to the stop mode is made, the mode can be released with input according to the setting of the interrupt input sources of external interrupts "H" level, "L" level, and rising edge, and falling edge.
Page 185 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.8 Notes on Using the Low-power Consumption Mode MB90930 Series ■ Notes on Accessing to the Low-power Consumption Mode Control Register (LPMCR) for the Transition to the Standby Mode ● When the low-power consumption mode control register (LPMCR) is accessed with the assembler language: •...
Page 186 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.8 Notes on Using the Low-power Consumption Mode MB90930 Series FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 187: Chapter 7 Mode Setting
CHAPTER 7 MODE SETTING This chapter explains the operation mode and memory access mode. 7.1 Mode Setting 7.2 Mode Pins (MD2 to MD0) 7.3 Mode Data CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 188: Mode Setting
CHAPTER 7 MODE SETTING 7.1 Mode Setting MB90930 Series Mode Setting MC-16LX has various modes for access methods and access areas.Each mode is set according to the setting of mode pins at reset and the mode- fetched mode data. ■ Mode Setting...
Page 189: Mode Pins (Md2 To Md0)
Flash serial write mode Flash writer write mode Set MD2 to MD0: 0=Vss, 1=Vcc. Note: In the MB90930 series, the mode pins are used in the single chip mode only. Therefore, set the MD2 to MD0 to "011 ". CM44-10150-1E...
Page 190: Mode Data
Table 7.3-1 Bus Mode Setting Bits and Functions Function Single chip mode (Setting prohibited) Note: In the MB90930 series, the mode data is used in th e single chip mode only. Therefore, set the M1 and MD0 to "00 ". FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 191 Table 7.3-2 shows the relationship between mode pins and mode data. Table 7.3-2 Relationship between Mode Pins and Mode Data Mode Single chip mode Note: In the MB90930 series, mode pins are used in the single chip mode only. CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 192 CHAPTER 7 MODE SETTING 7.3 Mode Data MB90930 Series FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 193: Chapter 8 I/O Ports
8.8 Port 5 8.9 Port 6 8.10 Port 7 8.11 Port 8 8.12 Port 9 8.13 Port C 8.14 Port D 8.15 Port E 8.16 Input Level Select Registers (PIL0 to PIL2) 8.17 Sample Program for I/O Ports CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 194: I/O Ports
I/O Ports The I/O ports can be used as general-purpose I/O ports (parallel I/O ports). The number of ports for the MB90930 series is 13 ports (93 pins). Each port is used both for peripheral functions and for providing input/output pins.
Page 195 CHAPTER 8 I/O PORTS 8.1 I/O Ports MB90930 Series Table 8.1-1 shows the list of functions of each port. Table 8.1-1 List of Functions of Each Port (1 / 2) Port Output Pin name Input format Function bit7 bit6 bit5...
Page 196 CHAPTER 8 I/O PORTS 8.1 I/O Ports MB90930 Series Table 8.1-1 List of Functions of Each Port (2 / 2) Port Output Pin name Input format Function bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name format General- purpose output port...
Page 197: Assignment Of Registers And Pins Shared With External Pins
CHAPTER 8 I/O PORTS 8.2 Assignment of Registers and Pins Shared with External Pins MB90930 Series Assignment of Registers and Pins Shared with External Pins The registers related to I/O port setting are listed ■ List of I/O Port Registers Table 8.2-1 shows the list of registers of each port.
Page 198 CHAPTER 8 I/O PORTS 8.2 Assignment of Registers and Pins Shared with External Pins MB90930 Series Table 8.2-1 List of Registers of Each Port (2 / 2) Register name Read/write Address Initial value 00001C 00000000 Port C direction register (DDRC)
Page 199: Port 0
CHAPTER 8 I/O PORTS 8.3 Port 0 MB90930 Series Port 0 Port 0 is a general-purpose I/O port that is also used for peripheral function I/O port. The use of each pin can be switched per bit between the peripheral function and the port.
Page 200 CHAPTER 8 I/O PORTS 8.3 Port 0 MB90930 Series ■ Pin Block Diagram for Port 0 Figure 8.3-1 shows the pin block diagram for Port 0. Figure 8.3-1 Pin Block Diagram for Port 0 Peripheral function output Peripheral function PDR (Port data register)
Page 201: Port 0 Registers (Pdr0, Ddr0)
CHAPTER 8 I/O PORTS 8.3 Port 0 MB90930 Series 8.3.1 Port 0 Registers (PDR0, DDR0) This section describes the registers for Port 0. ■ Functions of Port 0 Registers ● Port 0 data register (PDR0) The PDR0 register indicates the pin states.
Page 202: Description Of Port 0 Operation
CHAPTER 8 I/O PORTS 8.3 Port 0 MB90930 Series 8.3.2 Description of Port 0 Operation This section describes the operation of Port 0. ■ Operation of Port 0 ● Operation as an output port With the corresponding DDR0 register bit set to "1", the port works as an output port.
Page 203 CHAPTER 8 I/O PORTS 8.3 Port 0 MB90930 Series ● Operation for the stop and time-base timer modes If the pin state specification bit of the low-power consumption mode control register (SPL in LPMCR) is "1" when a transition to the stop mode or time-base timer mode occurs, the pins are set to high impedance.
Page 204: Port 1
CHAPTER 8 I/O PORTS 8.4 Port 1 MB90930 Series Port 1 Port 1 is a general-purpose I/O port that is also used for a peripheral function input port. The use of each pin can be switched per bit between the peripheral function and the port.
Page 205 CHAPTER 8 I/O PORTS 8.4 Port 1 MB90930 Series ■ Pin Block Diagram for Port 1 Figure 8.4-1 shows the pin block diagram for Port 1. Figure 8.4-1 Pin Block Diagram for Port 1 Peripheral Peripheral function input function output...
Page 206: Port 1 Registers (Pdr1, Ddr1)
CHAPTER 8 I/O PORTS 8.4 Port 1 MB90930 Series 8.4.1 Port 1 Registers (PDR1, DDR1) This section describes the registers for Port 1. ■ Functions of Port 1 Registers ● Port 1 data register (PDR1) The PDR1 register indicates the pin states.
Page 207: Description Of Port 1 Operation
CHAPTER 8 I/O PORTS 8.4 Port 1 MB90930 Series 8.4.2 Description of Port 1 Operation This section describes the operation of Port 1. ■ Operation of Port 1 ● Operation as an output port With the corresponding DDR1 register bit set to "1", the port works as an output port.
Page 208 CHAPTER 8 I/O PORTS 8.4 Port 1 MB90930 Series ● Reset operation At CPU reset, the DDR1 register value is cleared. Thus, all the output buffers are set to "OFF" (input port), and also as the pull-up resistor is cut, the pins are set to "high-impedance".
Page 209: Port 2
CHAPTER 8 I/O PORTS 8.5 Port 2 MB90930 Series Port 2 Port 2 is a general-purpose I/O port that is also used for peripheral function I/O port. The use of each pin can be switched per bit between the peripheral function and the port.
Page 210 CHAPTER 8 I/O PORTS 8.5 Port 2 MB90930 Series ■ Pin Block Diagram for Port 2 Figure 8.5-1 shows the pin block diagram for Port 2. Figure 8.5-1 Pin Block Diagram for Port 2 Peripheral function output LCD output Peripheral function...
Page 211: Port 2 Data Register (Pdr2, Ddr2)
CHAPTER 8 I/O PORTS 8.5 Port 2 MB90930 Series 8.5.1 Port 2 Data Register (PDR2, DDR2) This section describes the registers for Port 2. ■ Functions of Port 2 Registers ● Port 2 data register (PDR2) The PDR2 register indicates the pin states.
Page 212: Description Of Port 2 Operation
CHAPTER 8 I/O PORTS 8.5 Port 2 MB90930 Series 8.5.2 Description of Port 2 Operation This section describes the operation of Port 2. ■ Operations of Port 2 ● Operation as an output port With the corresponding DDR2 register bit set to "1", the port works as an output port.
Page 213 CHAPTER 8 I/O PORTS 8.5 Port 2 MB90930 Series ● Operation for the stop and time-base timer modes If the pin state specification bit of the low-power consumption mode control register (SPL in LPMCR) is "1" when a transition to the stop mode or time-base timer mode occurs, the pins are set to high impedance.
Page 214: Port 3
CHAPTER 8 I/O PORTS 8.6 Port 3 MB90930 Series Port 3 Port 3 is a general-purpose I/O port that is also used for peripheral function I/O port. The use of each pin can be switched per bit between the peripheral function and the port.
Page 215 CHAPTER 8 I/O PORTS 8.6 Port 3 MB90930 Series ■ Pin Block Diagram for Port 3 Figure 8.6-1 shows the pin block diagram for Port 3. Figure 8.6-1 Pin Block Diagram for Port 3 Peripheral function output Peripheral function LCD output...
Page 216: Port 3 Registers (Pdr3, Ddr3)
CHAPTER 8 I/O PORTS 8.6 Port 3 MB90930 Series 8.6.1 Port 3 Registers (PDR3, DDR3) This section describes the registers for Port 3. ■ Functions of Port 3 Registers ● Port 3 data register (PDR3) The PDR3 register indicates the pin states.
Page 217: Description Of Port 3 Operation
CHAPTER 8 I/O PORTS 8.6 Port 3 MB90930 Series 8.6.2 Description of Port 3 Operation This section describes the operation of Port 3. ■ Operation of Port 3 ● Operation as an output port With the corresponding DDR3 register bit set to "1", the port works as an output port.
Page 218 CHAPTER 8 I/O PORTS 8.6 Port 3 MB90930 Series ● Operation for the stop and time-base timer modes If the pin state specification bit of the low-power consumption mode control register (SPL in LPMCR) is "1" when a transition to the stop mode or time-base timer mode occurs, the pins are set to high impedance.
Page 219: Port 4
CHAPTER 8 I/O PORTS 8.7 Port 4 MB90930 Series Port 4 Port 4 is a general-purpose I/O port that is also used for a peripheral function I/O port. The use of each pin can be switched per bit between the peripheral function and the port.
Page 220 CHAPTER 8 I/O PORTS 8.7 Port 4 MB90930 Series ■ Pin Block Diagram for Port 4 Figure 8.7-1 shows the pin block diagram for Port 4. Figure 8.7-1 Pin Block Diagram for Port 4 Peripheral function output Peripheral function LCD output...
Page 221: Port 4 Registers (Pdr4, Ddr4)
CHAPTER 8 I/O PORTS 8.7 Port 4 MB90930 Series 8.7.1 Port 4 Registers (PDR4, DDR4) This section describes the registers for Port 4. ■ Functions of Port 4 Registers ● Port 4 data register (PDR4) The PDR4 register indicates the pin states.
Page 222: Description Of Port 4 Operation
CHAPTER 8 I/O PORTS 8.7 Port 4 MB90930 Series 8.7.2 Description of Port 4 Operation This section describes the operation of Port 4. ■ Operation of Port 4 ● Operation as an output port With the corresponding DDR4 register bit set to "1", the port works as an output port.
Page 223 CHAPTER 8 I/O PORTS 8.7 Port 4 MB90930 Series ● Operation for the stop and time-base timer modes If the pin state specification bit of the low-power consumption mode control register (SPL in LPMCR) is "1" when a transition to the stop mode or time-base timer mode occurs, the pins are set to high impedance.
Page 224: Port 5
CHAPTER 8 I/O PORTS 8.8 Port 5 MB90930 Series Port 5 Port 5 is a general-purpose I/O port that is also used for a peripheral function I/O port. The use of each pin can be switched per bit between the peripheral function and the port.
Page 225 CHAPTER 8 I/O PORTS 8.8 Port 5 MB90930 Series ■ Port 5 Pins The I/O pins of Port 5 are also used for peripheral function input pins. Therefore, if used as peripheral function input/output pins, they must not be used as general-purpose I/O ports.
Page 226 CHAPTER 8 I/O PORTS 8.8 Port 5 MB90930 Series ■ Pin Block Diagram for Port 5 Figure 8.8-1 shows the pin block diagram for Port 5. Figure 8.8-1 Pin Block Diagram for Port 5 Peripheral Peripheral function input function output...
Page 227: Port 5 Registers (Pdr5, Ddr5)
CHAPTER 8 I/O PORTS 8.8 Port 5 MB90930 Series 8.8.1 Port 5 Registers (PDR5, DDR5) This section describes the registers for Port 5. ■ Functions of Port 5 Registers ● Port 5 data register (PDR5) The PDR5 register indicates the pin states.
Page 228: Description Of Port 5 Operation
CHAPTER 8 I/O PORTS 8.8 Port 5 MB90930 Series 8.8.2 Description of Port 5 Operation This section describes the operation of Port 5. ■ Operation of Port 5 ● Operation as an output port With the corresponding DDR5 register bit set to "1", the port works as an output port.
Page 229 CHAPTER 8 I/O PORTS 8.8 Port 5 MB90930 Series ● Reset operation At CPU reset, the DDR5 register value is cleared. Thus, all the output buffers are set to "OFF" (input port) and the pins are set to high impedance.
Page 230: Port 6
CHAPTER 8 I/O PORTS 8.9 Port 6 MB90930 Series Port 6 Port 6 is a general-purpose I/O port that is also used as an analog input of A/D converter. The use of each pin can be switched per bit between the analog input and the port.
Page 231 CHAPTER 8 I/O PORTS 8.9 Port 6 MB90930 Series ■ Pin Block Diagram for Port 6 Figure 8.9-1 shows the pin block diagram of Port 6. Figure 8.9-1 Pin Block Diagram for Port 6 ADER6 Analog input PDR (Port data register)
Page 232: Port 6 Registers (Pdr6, Ddr6, Ader6)
CHAPTER 8 I/O PORTS 8.9 Port 6 MB90930 Series 8.9.1 Port 6 Registers (PDR6, DDR6, ADER6) This section describes the registers for Port 6. ■ Functions of Port 6 Registers ● Port 6 data register (PDR6) The PDR6 register indicates the pin states.
Page 233: Description Of Port 6 Operation
CHAPTER 8 I/O PORTS 8.9 Port 6 MB90930 Series 8.9.2 Description of Port 6 Operation This section describes the operation of Port 6. ■ Operation of Port 6 ● Operation as an output port With the corresponding DDR6 register bit set to "1", the port works as an output port.
Page 234 CHAPTER 8 I/O PORTS 8.9 Port 6 MB90930 Series ● Operation for the stop and time-base timer modes If the pin state specification bit of the low-power consumption mode control register (SPL in LPMCR) is "1" when a transition to the stop mode or time-base timer mode occurs, the pins are set to high impedance.
Page 235: Port 7
CHAPTER 8 I/O PORTS 8.10 Port 7 MB90930 Series 8.10 Port 7 Port 7 is a general-purpose output-only port that is also used for a peripheral function port. The use of each pin can be switched per bit between the peripheral function and the port.
Page 236 CHAPTER 8 I/O PORTS 8.10 Port 7 MB90930 Series Table 8.10-1 Port 7 Pins Type o f Port input/output Circuit Pin name Port function Peripheral function name type Input Output P70/ Analog PWM1P0/ PWM1P0 input 8 P71/ Analog PWM1M0/ PWM1M0...
Page 237 CHAPTER 8 I/O PORTS 8.10 Port 7 MB90930 Series ■ Pin Block Diagram for Port 7 Figure 8.10-1 shows the pin block diagram for Port 7. Figure 8.10-1 Pin Block Diagram for Port 7 Peripheral Analog input function output Peripheral function...
Page 238: Port 7 Registers (Pdr7, Ddr7, Ader7)
CHAPTER 8 I/O PORTS 8.10 Port 7 MB90930 Series 8.10.1 Port 7 Registers (PDR7, DDR7, ADER7) This section describes the registers for Port 7. ■ Functions of Port 7 Registers ● Port 7 data register (PDR7) The PDR7 register indicates the pin states.
Page 239 CHAPTER 8 I/O PORTS 8.10 Port 7 MB90930 Series Table 8.10-3 Functions of Port 7 Registers Register Data When reading When writing R/W Address Initial value name When PWM output enabled: Sets the output latch Output value of peripheral to "0", and outputs "L"...
Page 240: Description Of Port 7 Operation
CHAPTER 8 I/O PORTS 8.10 Port 7 MB90930 Series 8.10.2 Description of Port 7 Operation This section describes the operation of Port 7. ■ Operation of Port 7 ● Operation as an output port Any data written to the PDR7 register is retained in the PDR output latch and then output to the pins as it is.
Page 241 CHAPTER 8 I/O PORTS 8.10 Port 7 MB90930 Series Table 8.10-5 Priority of Pin Output of Port 7 Pin name Priority 1 Priority 2 Priority 3 Priority 4 P70/ PWM1P0/AN8 PWM1P0 P71/ PWM1M0/AN9 PWM1M0 P72/ PWM2P0/AN10 PWM2P0 P73/ PWM2M0/AN11 PWM2M0...
Page 242: Port 8
CHAPTER 8 I/O PORTS 8.11 Port 8 MB90930 Series 8.11 Port 8 Port 8 is a general-purpose output-only port that is also used for a peripheral function port. The use of each pin can be switched per bit between the peripheral function and the port.
Page 243 CHAPTER 8 I/O PORTS 8.11 Port 8 MB90930 Series Table 8.11-1 Port 8 Pins Type of input/ Port output Circuit Pin name Port function Peripheral function name type Input Output P80/ Analog PWM1P2/ PWM1P2 AN16 input 16 AN16 P81/ Analog...
Page 244 CHAPTER 8 I/O PORTS 8.11 Port 8 MB90930 Series ■ Pin Block Diagram for Port 8 Figure 8.11-1 shows the pin block diagram for Port 8. Figure 8.11-1 Pin Block Diagram for Port 8 Peripheral Analog input function output Peripheral function...
Page 245: Port 8 Registers (Pdr8, Ddr8, Ader8)
CHAPTER 8 I/O PORTS 8.11 Port 8 MB90930 Series 8.11.1 Port 8 Registers (PDR8, DDR8, ADER8) This section describes the registers for Port 8. ■ Functions of Port 8 Registers ● Port 8 data register (PDR8) The PDR8 register indicates the pin states.
Page 246 CHAPTER 8 I/O PORTS 8.11 Port 8 MB90930 Series Table 8.11-3 Functions of Port 8 Registers Register Data When reading When writing Address Initial value name When PWM output enabled: Sets the output latch Output value of peripheral to "0", and outputs function is "L"...
Page 247: Description Of Port 8 Operation
CHAPTER 8 I/O PORTS 8.11 Port 8 MB90930 Series 8.11.2 Description of Port 8 Operation This section describes the operation of Port 8. ■ Operation of Port 8 ● Operation as an output port With the corresponding DDR8 register bit set to "1", the port works as an output port.
Page 248 CHAPTER 8 I/O PORTS 8.11 Port 8 MB90930 Series Table 8.11-5 Priority of Pin Output of Port 8 Pin name Priority 1 Priority 2 Priority 3 Priority 4 P80/PWM1P2/AN16 PWM1P2 P81/PWM1M2/AN17 PWM1M2 P82/PWM2P2/AN18 PWM2P2 P83/PWM2M2/AN19 PWM2M2 P84/PWM1P3/AN20 PWM1P3 P85/PWM1M3/AN21 PWM1M3...
Page 249: Port 9
CHAPTER 8 I/O PORTS 8.12 Port 9 MB90930 Series 8.12 Port 9 Port 9 is a general-purpose I/O port that is also used for a peripheral function I/O port. The use of each pin can be switched per bit between the peripheral function and the port.
Page 250 CHAPTER 8 I/O PORTS 8.12 Port 9 MB90930 Series ■ Pin Block Diagram for Port 9 Figure 8.12-1 shows the pin block diagram for Port 9. Figure 8.12-1 Pin Block Diagram for Port 9 Peripheral function output LCD Vn Peripheral function...
Page 251: Registers For Port 9 (Pdr9, Ddr9)
CHAPTER 8 I/O PORTS 8.12 Port 9 MB90930 Series 8.12.1 Registers for Port 9 (PDR9, DDR9) This section describes the registers for Port 9. ■ Functions of Port 9 Registers ● Port 9 data register (PDR9) The PDR9 register indicates the pin states.
Page 252: Description Of Port 9 Operation
CHAPTER 8 I/O PORTS 8.12 Port 9 MB90930 Series 8.12.2 Description of Port 9 Operation This section describes the operation of Port 9. ■ Operation of Port 9 ● Operation as an output port With the corresponding DDR9 register bit set to "1", the port works as an output port.
Page 253 CHAPTER 8 I/O PORTS 8.12 Port 9 MB90930 Series ● Operation for the stop and time-base timer modes If the pin state specification bit of the low-power consumption mode control register (SPL in LPMCR) is "1" when a transition to the stop mode or time-base timer mode occurs, the pins are set to high impedance.
Page 254: Port C
CHAPTER 8 I/O PORTS 8.13 Port C MB90930 Series 8.13 Port C Port C is a general-purpose I/O port that is also used for a peripheral function input port. The use of each pin can be switched per bit between the peripheral function and the port.
Page 255 CHAPTER 8 I/O PORTS 8.13 Port C MB90930 Series ■ Port C Pins The pins of Port C pins are also used for peripheral function input/output pins. If used as peripheral function I/O pins, they must not be used as general purpose I/O ports. Table 8.13-1 shows the pins of Port C.
Page 256 CHAPTER 8 I/O PORTS 8.13 Port C MB90930 Series ■ Pin Block Diagram for Port C Figure 8.13-1 shows the pin block diagram for Port C. Figure 8.13-1 Pin Block Diagram for Port C Peripheral Peripheral function input function output...
Page 257: Registers For Port C (Pdrc, Ddrc)
CHAPTER 8 I/O PORTS 8.13 Port C MB90930 Series 8.13.1 Registers for Port C (PDRC, DDRC) This section describes the registers for Port C. ■ Functions of Port C Registers ● Port C data register (PDRC) The PDRC register indicates the pin states.
Page 258: Description Of Port C Operation
CHAPTER 8 I/O PORTS 8.13 Port C MB90930 Series 8.13.2 Description of Port C Operation This section describes the operation of Port C. ■ Operation of Port C ● Operation as an output port With the corresponding DDRC register bit set to "1", the port works as an output port.
Page 259 CHAPTER 8 I/O PORTS 8.13 Port C MB90930 Series ● Reset operation At CPU reset, the DDRC register value is cleared. Thus, all the output buffers are set to "OFF" (input port), and, the pins are set to high impedance.
Page 260 CHAPTER 8 I/O PORTS 8.13 Port C MB90930 Series Table 8.13-5 Priority of Pin Output of Port C Pin name Priority 1 Priority 2 Priority 3 Priority 4 PC0/SIN0/INT4 PC1/SOT0/INT5/IN3 SOT0 PC2/SCK0/INT6/IN2 SCK0 PC3/SIN1/INT7 PC4/SOT1 SOT1 PC5/SCK1/TRG SCK1 PC6/PPG0/TOT1/IN7 PPG0...
Page 261: Port D
CHAPTER 8 I/O PORTS 8.14 Port D MB90930 Series 8.14 Port D Port D is a general-purpose I/O port that is also used for a peripheral function I/ O port. The use of each pin can be switched per bit between the peripheral function and the port.
Page 262 CHAPTER 8 I/O PORTS 8.14 Port D MB90930 Series Table 8.14-1 Port D Pins Type of Input/Output Peripheral Circuit Port name Pin name Port function function type Input Output CMOS/ CMOS Hysteresis/ PD0/SIN2 PD0 SIN2 Automotive level PD1/ SOT2 SOT2...
Page 263 CHAPTER 8 I/O PORTS 8.14 Port D MB90930 Series ■ Pin Block Diagram for Port D Figure 8.14-1 shows the pin block diagram for Port D. Figure 8.14-1 Pin Block Diagram for Port D Peripheral Peripheral function input function output...
Page 264: Registers For Port D (Pdrd, Ddrd)
CHAPTER 8 I/O PORTS 8.14 Port D MB90930 Series 8.14.1 Registers for Port D (PDRD, DDRD) This section describes the registers for Port D. ■ Functions of Port D Registers ● Port D data register (PDRD) The PDRD register indicates the pin states.
Page 265: Description Of Port D Operation
CHAPTER 8 I/O PORTS 8.14 Port D MB90930 Series 8.14.2 Description of Port D Operation This section describes the operation of Port D. ■ Operation of Port D ● Operation as an output port With the corresponding DDRD register bit set to "1", the port works as an output port.
Page 266 CHAPTER 8 I/O PORTS 8.14 Port D MB90930 Series ● Operation for the stop and time-base timer modes If the pin state specification bit of the low-power consumption mode control register (SPL in LPMCR) is "1" when a transition to the stop mode or time-base timer mode occurs, the pins are set to high impedance.
Page 267: Port E
CHAPTER 8 I/O PORTS 8.15 Port E MB90930 Series 8.15 Port E Port E is a general-purpose I/O port that is also used for a peripheral function I/O port. The use of each pin can be switched per bit between the peripheral function and the port.
Page 268 CHAPTER 8 I/O PORTS 8.15 Port E MB90930 Series ■ Pin Block Diagram for Port E Figure 8.15-1 shows the pin block diagram for Port E. Figure 8.15-1 Pin Block Diagram for Port E Peripheral Peripheral function input function output...
Page 269: Registers For Port E (Pdre, Ddre)
CHAPTER 8 I/O PORTS 8.15 Port E MB90930 Series 8.15.1 Registers for Port E (PDRE, DDRE) This section describes the registers for Port E. ■ Functions of Port E Registers ● Port E data register (PDRE) The PDRE register indicates the pin states.
Page 270: Description Of Port E Operation
CHAPTER 8 I/O PORTS 8.15 Port E MB90930 Series 8.15.2 Description of Port E Operation This section describes the operation of Port E ■ Operation of Port E ● Operation as an output port With the corresponding DDRE register bit set to "1", the port works as an output port.
Page 271 CHAPTER 8 I/O PORTS 8.15 Port E MB90930 Series ● Operation for the stop and time-base timer modes If the pin state specification bit of the low-power consumption mode control register (SPL in LPMCR) is "1" when a transition to the stop mode or time-base timer mode occurs, the pins are set to high impedance.
Page 272: Input Level Select Registers (Pil0 To Pil2)
CHAPTER 8 I/O PORTS 8.16 Input Level Select Registers (PIL0 to PIL2) MB90930 Series 8.16 Input Level Select Registers (PIL0 to PIL2) The input level select registers allow to switch from Automotive input levels (V =0.8V /0.5V ) to CMOS Hysteresis input levels (V =0.8V...
Page 273 CHAPTER 8 I/O PORTS 8.16 Input Level Select Registers (PIL0 to PIL2) MB90930 Series ● bit12: Reserved bit This is a reserved bit. Always write "0" to this bit. ● bit11:ILSIN1 Selects the input level of serial input pin of UART1(SIN1).
Page 274 CHAPTER 8 I/O PORTS 8.16 Input Level Select Registers (PIL0 to PIL2) MB90930 Series ● bit3: ILSIN2 These bits are used to select the input level for the serial input pin (SIN2) of UART2. When set to "0": Sets to the level specified in PIL2 register.
Page 275: Sample Program For I/O Ports
CHAPTER 8 I/O PORTS 8.17 Sample Program for I/O Ports MB90930 Series 8.17 Sample Program for I/O Ports A sample program that uses the I/O port is shown below. ■ Sample Program for I/O Ports ● Specification of processing On ports 0 and 1, all 7-segment LEDs (8-segment if Dp is included) are on.
Page 276 CHAPTER 8 I/O PORTS 8.17 Sample Program for I/O Ports MB90930 Series FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 277: Watchdog Timer/Time-Base Timer/Watch Timer (Sub Clock)
9.2 Block Diagrams of Watchdog Timer/Time-base Timer/ Watch Timer 9.3 List of Registers for Watchdog Timer/Time-base Timer/ Watch Timer 9.4 Operation of Watchdog Timer/Time-base Timer/Watch Timer 9.5 Notes on Using the Watchdog Timer/Time-base Timer 9.6 Program Example for Watchdog Timer/Time-base Timer CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 278: Outline Of Watchdog Timer/Time-Base Timer/Watch Timer
The watch timer, which is a timer for the watchdog timer's clock source and sub clock oscillation stabilization time waiting, has a function of an interval timer by regularly generating an interrupt. The watch timer uses the sub clock irrespective of the MCS bit in CKSCR and SCS bit. FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 279: Block Diagrams Of Watchdog Timer/Time-Base Timer/Watch Timer
Power-on reset, Stopping the sub clock WTC2 Selector WTC0 Watch timer WTIE Clock input WTOF WTRES sub clock Clock interrupt WDTC From power-on PONR generation − WRST RST pin ERST From LPMCR SRST register's RST bit CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 280: List Of Registers For Watchdog Timer/Time-Base Timer/Watch Timer
− − Initial value → Watch timer control register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Address: 0000AA WDCS WTIE WTOF WTC2 WTC1 WTC0 Initial value → Read only Write only R/W : Readable/Writable Undefined FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 281: Watchdog Timer Control Register (Wdtc)
Table 9.3-1 PONR, WRST, ERST, and SRST (reset Source Bits) Reset source PONR WRST ERST SRST Power-on Watchdog Timer External pin (RST input) CPU operation detection reset Low-voltage detection reset RST bit (software reset) : Previous value is retained. -: Undefined CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 282 Approx. 7.0 s Approx. 9.0 s Approx. 14.0 s Approx. 18.0 s * : The maximum interval time is the value available when the watchdog timer is operating and the time-base timer or watch timer is not reset. FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 283: Time-Base Timer Control Register (Tbtc)
• Transition from sub clock mode to PLL clock mode • Transition from main clock mode to PLL clock mode • Writing "0" to the TBR bit • Reset Writing "1" has no effect. Reading by read-modify-write (RMW) instructions always reads "1". CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 284 Table 9.3-3 Interval Time and Cycle Count of TBC1 and TBC0 Interval time Oscillation clock (source oscillation) TBC1 TBC0 for source oscillation: 4 MHz cycle count 1.024 ms cycles 4.096 ms cycles 16.384 ms cycles 131.072 ms cycles FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 285: Watch Timer Control Register (Wtc)
The WTIE bit enables interval interrupts by the watch wait timer. This bit is set to "1" to enable interrupts or set to "0" to disable them. This bit is initialized to "0" by reset. This bit can be read and written. CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 286 Table 9.3-4 Selection of the Watch Timer Interval WTC2 WTC1 WTC0 Interval Time * 31.25ms 62.5ms 125ms 250ms 500ms 1.00s 2.00s 4.00s * : The value of the interval time applies to a sub clock oscillation of 32.768 kHz. FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 287: Operation Of Watchdog Timer/Time-Base Timer/Watch Timer
The watch timer provides such timer functions as acting the watchdog timer's clock source, and providing the oscillation stabilization wait time for sub clock. It also provides an interval interrupt function by generating interrupts at regular intervals. CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 288: Watchdog Timer Operation
Figure 9.4-2 shows the relationship between the timing when the watchdog timer is cleared and its interval time. The interval time varies depending on the timing for clearing the watchdog timer, which requires 3.5 to 4.5 times the count clock interval. FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 289 [Maximum interval time] If WTE bit is cleared immediately after the rise of count clock Count start Counter clear Count clock a Divide-by-2 value b Divide-by-2 value c Count enabled Reset signal 9 x (count clock interval/2) WTE bit clear Watchdog reset occurs CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 290: Operation Of Time-Base Timer
"0" to clear the interrupt request. In addition, the TBOF bit is set if the specified bit overflows, irrespective of the TBIE bit value. When the TBOF bit is set to "1" and the TBIE bit is switched from "disabled" to "enabled" ("0" to "1"), an interrupt request is generated immediately. FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 291 PLL clock mode occurs, the time-base timer counter is not cleared and indicates a time on the way of counting. Table 9.4-2 shows the clearing of the time-base counter and the oscillation stabilization wait time. CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 292 (SCS=0 stabilization wait time Transition from sub clock mode to Main clock oscillation → PLL clock mode (MCS=0, SCS=0 stabilization wait time Releasing time-base timer mode None Releasing sleep mode None Y: Used N: Not used FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 293: Operation Of Watch Timer
Table 9.4-3 shows the watch timer's interrupts and EI Table 9.4-3 Watch Timer Interrupts and EI Interrupt level setting register Vector table address Interrupt Register name Address Lower Upper Bank #30 (1E 0000B9 FFFF84 FFFF85 FFFF86 ICR09 × ×: Not available CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 294 ICR09 is commonly used by real-time watch timer interrupts and PPG timer 2 to PPG timer 5 interrupts, and the interrupt level is the same. • The watch timer cannot use the extended intelligent I/O service (EI OS). FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 295: Notes On Using The Watchdog Timer/Time-Base Timer
Effects of clearing the time-base timer The following operations are affected by clearing the time-base timer's counter. • When an interval timer function (interval interrupt) by the time-base timer is used • When the watchdog timer is used. CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 296 1/2 an interval at maximum. Although the watchdog timer's clock is also provided in the state after initialization, the watchdog timer's counter is cleared as well, causing the watchdog timer to operate with the standard interval. FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 297 Interval interrupt sleep released STP bit (LPMCR register) Stop cleared by external interrupt If the interval time selection bits (TBTC: TBC1, TBC0) in the time-base timer control register is set to "11 " /HCLK). : Oscillation stabilization wait time CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 298: Program Example For Watchdog Timer/Time-Base Timer
User process MAIN ;Loop by the period shorter than the ;interval time of the watchdog timer CODE ENDS ;---------Vector setting------------------------------------------------------ VECT CSEG ABS=0FFH 0FFDCH ;Reset vector setting START ;Set to single-chip mode VECT ENDS ENDS START FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 299 ;Clear interrupt request flag User process RETI ;Return from interrupt CODE ENDS ;---------Vector setting------------------------------------------------------ VECT CSEG ABS=0FFH 0FF70H ;Setting vector to interrupt #35(23 WARI 0FFDCH ;Reset vector setting START ;Setting to single-chip mode VECT ENDS ENDS START CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 300 CHAPTER 9 WATCHDOG TIMER/ TIME-BASE TIMER/WATCH TIMER (Sub clock) 9.6 Program Example for Watchdog Timer/Time-base Timer MB90930Series FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 301: Chapter 10 Input Capture
CHAPTER 10 INPUT CAPTURE This chapter describes the input capture operation. 10.1 Outline of Input Capture 10.2 List of Input Capture Registers 10.3 Description of Operations CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 302: Outline Of Input Capture
CHAPTER 10 INPUT CAPTURE 10.1 Outline of Input Capture MB90930 Series 10.1 Outline of Input Capture The input capture unit consists of 1 16-bit free-run timer and 8 16-bit input captures. ■ Configuration of Input Capture ● Input capture (× 8) The input capture consists of 8 independent external input pins, their corresponding capture registers and control registers.
Page 303: Block Diagram Of Input Capture
CHAPTER 10 INPUT CAPTURE 10.1 Outline of Input Capture MB90930 Series 10.1.1 Block Diagram of Input Capture Input capture consists of the following blocks. ■ Block Diagram of Input Capture Figure 10.1-1 Block Diagram of Input Capture Unit 0 16-bit free-run timer...
Page 304 CHAPTER 10 INPUT CAPTURE 10.1 Outline of Input Capture MB90930 Series Figure 10.1-2 Block Diagram of Input Capture Unit 1 16-Bit free-run timer Edge detection circuit IN7/IN7R IN7/IN7R Input capture data register 7 (IPCP7) LIN-UART3 IN6/IN6R Input capture data register 6 (IPCP6)
Page 305: List Of Input Capture Registers
CHAPTER 10 INPUT CAPTURE 10.2 List of Input Capture Registers MB90930 Series 10.2 List of Input Capture Registers This section lists the input capture registers. ■ List of Registers for 16-bit Free-run Timer Section Figure 10.2-1 lists registers for the 16-bit free-run timer section.
Page 306 CHAPTER 10 INPUT CAPTURE 10.2 List of Input Capture Registers MB90930 Series ■ List of Registers for Input Capture Section Figure 10.2-2 lists of registers for the input capture section. Figure 10.2-2 List of Registers for Capture Section Input capture data register (Upper)
Page 307 CHAPTER 10 INPUT CAPTURE 10.2 List of Input Capture Registers MB90930 Series (Continued) Input capture edge register (Upper) bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 Address: 00006B IEI3 IEI2 ICE23 Initial value → Input capture edge register (Lower) bit15...
Page 308: Detailed Description Of The Input Capture Registers
CHAPTER 10 INPUT CAPTURE 10.2 List of Input Capture Registers MB90930 Series 10.2.1 Detailed Description of the Input Capture Registers There are three types of input capture registers: • Input capture register (IPCP0 to IPCP7) • Input capture control registers (ICS01/ICS23/ICS45/ICS67) •...
Page 309 CHAPTER 10 INPUT CAPTURE 10.2 List of Input Capture Registers MB90930 Series ■ Input Capture Control Status Register (ICS01/ICS23/ICS45/ICS67) Figure 10.2-4 Configuration of Input Capture Control Status Register (ICS01/ICS23/ICS45/ICS67) Input capture control status register (Upper) bit7 bit6 bit5 bit4 bit3...
Page 310 CHAPTER 10 INPUT CAPTURE 10.2 List of Input Capture Registers MB90930 Series [bit3 to bit0]: EGn1, EGn0 (n=7 to 0) These bits are used to select the polarity of a valid edge from the external input. They are also used for enabling input capture operation.
Page 311: Input Capture Edge Register (Ice)
CHAPTER 10 INPUT CAPTURE 10.2 List of Input Capture Registers MB90930 Series 10.2.2 Input Capture Edge Register (ICE) The input capture edge register has a function to indicate the selected edge direction and to select whether the input signal is input from either external pin or LIN-UART.
Page 312 CHAPTER 10 INPUT CAPTURE 10.2 List of Input Capture Registers MB90930 Series ■ Input Capture Edge Register (ICE) Figure 10.2-6 Input Capture Edge Register (ICE) bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 ICE01 Initial value Address: 000069 IEI1 IEI0...
Page 313 CHAPTER 10 INPUT CAPTURE 10.2 List of Input Capture Registers MB90930 Series Table 10.2-1 Functions of Input Capture Edge Register 01(ICE01) Bit name Function bit15 When reading: The value is undefined. Undefined bits When writing: No effect. bit13 ICUS1: This bit selects the input signal used as the trigger of input capture 1.
Page 314 CHAPTER 10 INPUT CAPTURE 10.2 List of Input Capture Registers MB90930 Series Table 10.2-3 Functions of Input Capture Edge Register 67(ICE67) Bit name Function bit15 When reading: The value is undefined. Undefined bits When writing: No effect. bit13 This bit selects the input signal used as the trigger of the input capture 7.
Page 315: Detailed Description Of 16-Bit Free-Run Timer Register
CHAPTER 10 INPUT CAPTURE 10.2 List of Input Capture Registers MB90930 Series 10.2.3 Detailed Description of 16-Bit Free-run Timer Register There are three types of 16-bit free-run timer registers: • Timer data register (TCDT) • Compare clear register (CPCLR) • Timer control status register (TCCSH, TCCSL) ■...
Page 316 CHAPTER 10 INPUT CAPTURE 10.2 List of Input Capture Registers MB90930 Series ■ Compare Clear Register (CPCLR) Figure 10.2-8 Configuration of the Compare Clear Register (CPCLR) Compare clear register (Upper) bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 Address: 000025...
Page 317 CHAPTER 10 INPUT CAPTURE 10.2 List of Input Capture Registers MB90930 Series Note: With th e in ternal clo ck select ed, specify the cou nt clock in bit2 t o bit 0 (CLK2 to CLK0 ). This count clock works as a base clock. If the clock is input from FRCK, set bit6 of DDR5 to "0".
Page 318 CHAPTER 10 INPUT CAPTURE 10.2 List of Input Capture Registers MB90930 Series [bit6]: IVFE This bit is an interrupt enable bit for the 16-bit free-run timer. If, with the IVFE bit set to "1", the interrupt flag (bit7: IVF) is set to "1", an interrupt is generated.
Page 319 CHAPTER 10 INPUT CAPTURE 10.2 List of Input Capture Registers MB90930 Series [bit2 to bit0]: CLK2 to CLK0 These bits are used to select a count clock for the 16-bit free-run timer. Because the clock changes immediately after setting the CLK bit, change the bit only when input capture is stopped.
Page 320: Description Of Operations
CHAPTER 10 INPUT CAPTURE 10.3 Description of Operations MB90930 Series 10.3 Description of Operations This section describes the operations of the input capture. ■ Description of Operations ● 16-Bit Free-run Timer The 16-bit free-run timer starts counting the counter value from "0000 when a reset has been H"...
Page 321: 16-Bit Input Capture
CHAPTER 10 INPUT CAPTURE 10.3 Description of Operations MB90930 Series 10.3.1 16-bit Input Capture The 16-bit input capture can generate an interrupt after fetching a 16-bit free- run timer value into the capture register upon detection of the specified valid edge.
Page 322: 16-Bit Free-Run Timer
CHAPTER 10 INPUT CAPTURE 10.3 Description of Operations MB90930 Series 10.3.2 16-bit Free-run Timer The 16-bit free-run timer starts counting the counter value from "0000 " when a reset has been released. This counter value is used as a reference time for the 16-bit input capture.
Page 323 CHAPTER 10 INPUT CAPTURE 10.3 Description of Operations MB90930 Series ■ Clear Timing for 16-bit Free-run Timer The counter is cleared by reset, by software, and by matching with the compare clear register. Counter clearing by reset is performed as soon as the clear source occurs, while counter clearing by matching with the compare clear register or by software is performed after synchronizing with the count timing.
Page 324 CHAPTER 10 INPUT CAPTURE 10.3 Description of Operations MB90930 Series FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 325: Chapter 11 16-Bit Reload Timer
11.3 Pins of 16-bit Reload Timer 11.4 Registers of 16-bit Reload Timer 11.5 Interrupts of 16-bit Reload Timer 11.6 Operation of 16-bit Reload Timer 11.7 Notes on Using 16-bit Reload Timer 11.8 Sample Program for 16-bit Reload Timer CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 326: Overview Of 16-Bit Reload Timer
CHAPTER 11 16-BIT RELOAD TIMER 11.1 Overview of 16-bit Reload Timer MB90930 Series 11.1 Overview of 16-bit Reload Timer The 16-bit reload timer has two modes: Internal clock mode (with countdown performed in synchronization with three types of internal clock), and event count mode (with countdown performed by detecting any pulse edge input to the external pin.
Page 327 CHAPTER 11 16-BIT RELOAD TIMER 11.1 Overview of 16-bit Reload Timer MB90930 Series ■ Event Count Mode (External Clock Mode) Event count mode is a function to start countdown at the selected valid edge (rising, falling, or both) when the edge is input to the TIN0/TIN1/TIN2/TIN3 pin. It is also used as an interval timer when using an external clock with a constant interval.
Page 328 CHAPTER 11 16-BIT RELOAD TIMER 11.1 Overview of 16-bit Reload Timer MB90930 Series ■ Interrupts and EI OS of 16-bit Reload Timer Table 11.1-3 lists the interrupts and EI OS from the 16-bit reload timer. Table 11.1-3 Interrupts and EI...
Page 329: Configuration Of 16-Bit Reload Timer
CHAPTER 11 16-BIT RELOAD TIMER 11.2 Configuration of 16-bit Reload Timer MB90930 Series 11.2 Configuration of 16-bit Reload Timer The 16-bit reload timer consists of the following 7 blocks: • Count clock generator circuit • Reload control circuit • Output control circuit •...
Page 330 CHAPTER 11 16-BIT RELOAD TIMER 11.2 Configuration of 16-bit Reload Timer MB90930 Series ● Count clock generator circuit The count clock generator circuit generates the count clock for the 16-bit reload timer from the machine clock or external input clock.
Page 331: Pins Of 16-Bit Reload Timer
CHAPTER 11 16-BIT RELOAD TIMER 11.3 Pins of 16-bit Reload Timer MB90930 Series 11.3 Pins of 16-bit Reload Timer This section shows the pins of the 16-bit reload timer and their block diagram. ■ Pins of 16-bit Reload Timer The pins of 16-bit reload timer can also be used for general-purpose ports. Table 11.3-1 shows the pin functions, I/O type, and settings for using the 16-bit reload timer.
Page 332 CHAPTER 11 16-BIT RELOAD TIMER 11.3 Pins of 16-bit Reload Timer MB90930 Series ■ Block Diagram of Pins for 16-bit Reload Timer Figure 11.3-1 shows a block diagram of the pins for the 16-bit reload timer. Figure 11.3-1 Block Diagram of Pins for 16-bit Reload Timer...
Page 333: Registers Of 16-Bit Reload Timer
CHAPTER 11 16-BIT RELOAD TIMER 11.4 Registers of 16-bit Reload Timer MB90930 Series 11.4 Registers of 16-bit Reload Timer This section lists the registers of the 16-bit reload timer. ■ Register List of 16-bit Reload Timer Figure 11.4-1 lists the registers of the 16-bit reload timer.
Page 334: Timer Control Status Registers, Upper (Tmcsr0H To Tmcsr3H)
CHAPTER 11 16-BIT RELOAD TIMER 11.4 Registers of 16-bit Reload Timer MB90930 Series 11.4.1 Timer Control Status Registers, Upper (TMCSR0H to TMCSR3H) Upper bit11 to bit8 and lower bit7 in the timer control status registers (TMCSR0 to TMCSR3) have functions to select the operation mode and set the operating condition of the 16-bit reload timer.
Page 335 CHAPTER 11 16-BIT RELOAD TIMER 11.4 Registers of 16-bit Reload Timer MB90930 Series Table 11.4-1 Functions of Upper Bits of Timer Control Status Registers (TMCSR0H to TMCSR3H) Bit name Function bit15 • Value at reading is not defined. Undefined bits •...
Page 336: Timer Control Status Registers, Lower (Tmcsr0L To Tmcsr3L)
CHAPTER 11 16-BIT RELOAD TIMER 11.4 Registers of 16-bit Reload Timer MB90930 Series 11.4.2 Timer Control Status Registers, Lower (TMCSR0L to TMCSR3L) Lower 7 bits of the timer control status registers (TMCSR0 to TMCSR3) have functions to set the operating condition, enable/disable the operation, control interrupts, and check the status of the 16-bit reload timer.
Page 337 CHAPTER 11 16-BIT RELOAD TIMER 11.4 Registers of 16-bit Reload Timer MB90930 Series Table 11.4-2 Functions of Lower Bits of Timer Control Status Registers (TMCSR0L to TMCSR3L) Bit name Function • Enables/disables outputs from the timer output pin. • When this bit is "0", the pin is used as general-purpose port; When this bit is "1", the...
Page 338: 16-Bit Timer Registers (Tmr0 To Tmr3)
CHAPTER 11 16-BIT RELOAD TIMER 11.4 Registers of 16-bit Reload Timer MB90930 Series 11.4.3 16-bit Timer Registers (TMR0 to TMR3) The 16-bit timer registers (TMR0 to TMR3) can always read the count value of the 16-bit down counter. ■ 16-bit Timer Registers (TMR0 to TMR3) Figure 11.4-4 shows the bit configuration of the 16-bit timer registers (TMR0 to TMR3).
Page 339: 16-Bit Reload Registers (Tmrlr0 To Tmrlr3)
CHAPTER 11 16-BIT RELOAD TIMER 11.4 Registers of 16-bit Reload Timer MB90930 Series 11.4.4 16-bit Reload Registers (TMRLR0 to TMRLR3) The 16-bit reload registers (TMRLR0 to TMRLR3) are used to set a reload value to the 16-bit down counter. The value written to these registers are loaded to the down counter and counted down.
Page 340: Interrupts Of 16-Bit Reload Timer
CHAPTER 11 16-BIT RELOAD TIMER 11.5 Interrupts of 16-bit Reload Timer MB90930 Series 11.5 Interrupts of 16-bit Reload Timer The 16-bit reload timer can generate an interrupt request due to counter underflow. The timer also supports the extended intelligent I/O service (EI OS).
Page 341: Operation Of 16-Bit Reload Timer
CHAPTER 11 16-BIT RELOAD TIMER 11.6 Operation of 16-bit Reload Timer MB90930 Series 11.6 Operation of 16-bit Reload Timer This section describes the 16-bit reload timer settings and counter operation states. ■ 16-bit Reload Timer Settings ● Settings of internal clock mode To operate as an interval timer, the settings shown in Figure 11.6-1 are required.
Page 342 CHAPTER 11 16-BIT RELOAD TIMER 11.6 Operation of 16-bit Reload Timer MB90930 Series ■ Counter Operation States The state of the counter is determined by the CNTE bit of the timer control status register (TMCSR0L to TMCSR3L, TMCSR0H to TMCSR3H) and the internal WAIT signal. States that can be set include the stop state (STOP state), activation trigger wait state (WAIT state), and operation state (RUN state).
Page 343: Internal Clock Mode (Reload Mode)
CHAPTER 11 16-BIT RELOAD TIMER 11.6 Operation of 16-bit Reload Timer MB90930 Series 11.6.1 Internal Clock Mode (Reload Mode) The counter operates in sync with the internal count clock to count down the 16-bit counter and generates the interrupt request to CPU with the counter underflow.
Page 344 CHAPTER 11 16-BIT RELOAD TIMER 11.6 Operation of 16-bit Reload Timer MB90930 Series ● External trigger operation When the valid edge (rising, falling, or both can be selectable) is input to the TIN pin, the counter is activated. Figure 11.6-5 shows the external trigger operation in reload mode.
Page 345: Internal Clock Mode (One Shot Mode)
CHAPTER 11 16-BIT RELOAD TIMER 11.6 Operation of 16-bit Reload Timer MB90930 Series 11.6.2 Internal Clock Mode (One Shot Mode) The counter operates in sync with the internal count clock to count down the 16-bit counter and generates the interrupt request to CPU with the counter underflow.
Page 346 CHAPTER 11 16-BIT RELOAD TIMER 11.6 Operation of 16-bit Reload Timer MB90930 Series ● External trigger operation When the valid edge (rising, falling, or both can be selectable) is input to the TIN0 to TIN3 pins, the counter is activated. Figure 11.6-8 shows the external trigger operation in one shot mode.
Page 347: Event Count Mode
CHAPTER 11 16-BIT RELOAD TIMER 11.6 Operation of 16-bit Reload Timer MB90930 Series 11.6.3 Event Count Mode The counter counts input edges from the TIN pin to count down the 16-bit counter and generates the interrupt request to CPU with the counter underflow.
Page 348 CHAPTER 11 16-BIT RELOAD TIMER 11.6 Operation of 16-bit Reload Timer MB90930 Series ● Operation in one shot mode −> FFFF If the counter value causes underflow (0000 ), the counter stops at FFFF . At this moment, the underflow request flag bit (UF) is set to "1", and the interrupt request occurs if the interrupt request output enable bit (INTE) is set to "1".
Page 349: Notes On Using 16-Bit Reload Timer
CHAPTER 11 16-BIT RELOAD TIMER 11.7 Notes on Using 16-bit Reload Timer MB90930 Series 11.7 Notes on Using 16-bit Reload Timer This section provides notes on using the 16-bit reload timer. ■ Notes on Using 16-bit Reload Timer ● Notes on setup by program Writing to the 16-bit reload registers (TMRLR0 to TMRLR3) must be performed with the counter stopped (TMCSR0 to TMCSR3:CNTE=0).
Page 350: Sample Program For 16-Bit Reload Timer
CHAPTER 11 16-BIT RELOAD TIMER 11.8 Sample Program for 16-bit Reload Timer MB90930 Series 11.8 Sample Program for 16-bit Reload Timer This section provides sample programs for internal clock mode and event count mode of the 16-bit reload timer. ■ Sample Program for Internal Clock Mode ●...
Page 351 CHAPTER 11 16-BIT RELOAD TIMER 11.8 Sample Program for 16-bit Reload Timer MB90930 Series ;----------Interrupt program----------------------------------- WARI: CLRB I:UF ;Clears the interrupt request flag User processing; RETI ; Return from interrupt. CODE ENDS ;----------Vector setting-------------------------------------- VECT CSEG ABS=0FFH 0FFB8H ;Set the vector to interrupt #17(11...
Page 352 CHAPTER 11 16-BIT RELOAD TIMER 11.8 Sample Program for 16-bit Reload Timer MB90930 Series ;edge, external output disabled ;Selects one shot mode, enables interrupt ;Clears the interrupt flag, and starts ;counter ILM, #07H ;Set ILM in PS to level 7 CCR, #40H ;Interrupt enabled...
Page 353: Chapter 12 Ppg Timer
CHAPTER 12 PPG TIMER This chapter describes the operations of PPG timer. 12.1 Overview of PPG Timer 12.2 Block Diagram of PPG Timer 12.3 Registers of PPG Timer 12.4 Interrupt of PPG Timer 12.5 PPG Timer Operation CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 354: Overview Of Ppg Timer
CHAPTER 12 PPG TIMER 12.1 Overview of PPG Timer MB90930 Series 12.1 Overview of PPG Timer The PPG timer consists of the prescaler, 16-bit down counter (x1), 16-bit data register with a buffer for setting cycle, 16-bit compare register with a buffer for setting a duty, and a pin control section.
Page 355: Block Diagram Of Ppg Timer
CHAPTER 12 PPG TIMER 12.2 Block Diagram of PPG Timer MB90930 Series 12.2 Block Diagram of PPG Timer This section shows a block diagram of PPG timer. ■ Block Diagram Figure 12.2-1 Block Diagram PCNTH0 to PCNTH5 CNTE STGR MDSE RTRG CKS1 CKS0 PGMS FSEL...
Page 356: Registers Of Ppg Timer
CHAPTER 12 PPG TIMER 12.3 Registers of PPG Timer MB90930 Series 12.3 Registers of PPG Timer This section describes the registers of the PPG timer. ■ Registers of PPG Timer Registers of PPG timer are described in detail next. FUJITSU MICROELECTRONICS LIMITED...
Page 357: List Of Ppg Timer Registers
CHAPTER 12 PPG TIMER 12.3 Registers of PPG Timer MB90930 Series 12.3.1 List of PPG Timer Registers This section describes the list of the PPG timer registers. ■ List of PPG Timer Registers PPG Control Status Register (upper) (PCNTH0 to PCNTH5)
Page 358 CHAPTER 12 PPG TIMER 12.3 Registers of PPG Timer MB90930 Series PPG Cycle Setting Register (upper) (PCSRH0 to PCSRH5) Address: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 CS15 CS14 CS13 CS12 CS11 CS10 CS09 CS08 ch.0 003923 ch.1 00392B ch.2 003933...
Page 359: Detailed Description Of Ppg Timer
CHAPTER 12 PPG TIMER 12.3 Registers of PPG Timer MB90930 Series 12.3.2 Detailed Description of PPG Timer The PPG timer has the following 5 registers. • PPG control status register (PCNT0 to PCNT5) • PPG down counter register (PDCR0 to PDCR5) •...
Page 360 CHAPTER 12 PPG TIMER 12.3 Registers of PPG Timer MB90930 Series [bit12] RTRG: Restart enable bit This bit enables to restart based on a trigger (software/external). This bit cannot be rewritten during operation. Restart disabled (initial value) Restart enable [bit11, bit10] CKS1,CKS0: Count clock selection bits These bits are used to select a counter clock for the 16-bit count down.
Page 361 CHAPTER 12 PPG TIMER 12.3 Registers of PPG Timer MB90930 Series [bit7, bit6] EGS1,EGS0: Trigger input edge selection bits These bits select a valid edge polarity of the external trigger. Writing "1" to the software trigger bit enables the software triggers in any mode selected.
Page 362 CHAPTER 12 PPG TIMER 12.3 Registers of PPG Timer MB90930 Series [bit1] POEN: PPG output enable bit Setting this bit to "1" enables PPG to output from the pin. General-purpose port (initial value) PPG output pin [bit0] OSEL: PPG output polarity specification bit This bit sets the polarity of the PPG output.
Page 363 CHAPTER 12 PPG TIMER 12.3 Registers of PPG Timer MB90930 Series ■ PPG Down Counter Register (PDCR) PDCR register can read the value of the 16-bit down counter. Access the PDCR register in words. PPG down counter register (upper) (PDCRH0 to PDCRH5)
Page 364 CHAPTER 12 PPG TIMER 12.3 Registers of PPG Timer MB90930 Series ■ PPG Duty Set Register (PDUT) The PDUT register sets the duty with a buffer. The transfer from the buffer is executed by a counter borrow or activation. If both values are the same in the cycle setting register and the duty setting register, all "H" for normal polarity or all "L"...
Page 365 CHAPTER 12 PPG TIMER 12.3 Registers of PPG Timer MB90930 Series [bit1, bit0] DIV1, DIV0: Division setting bits These bits set the division ratio of PPG ch.0. DIV1 DIV0 Division ratio 1/1 (initial value) Note: There are following limitations when the 1/2, 1/4, and 1/8 division setting is used.
Page 366: Interrupt Of Ppg Timer
CHAPTER 12 PPG TIMER 12.4 Interrupt of PPG Timer MB90930 Series 12.4 Interrupt of PPG Timer The PPG timer can generate an interrupt request by timer activation, counter borrow (cycle match), and duty match. The timer also supports the extended intelligent I/O service (EI OS).
Page 367 CHAPTER 12 PPG TIMER 12.4 Interrupt of PPG Timer MB90930 Series ■ EI OS Functions of PPG Timer The PPG timer has a circuit supporting EI OS. Thus, the PPG timer can activate EI OS by timer activation, counter borrow (cycle match), and duty match. However, EI...
Page 368: Ppg Timer Operation
CHAPTER 12 PPG TIMER 12.5 PPG Timer Operation MB90930 Series 12.5 PPG Timer Operation This section describes the PPG Timer Operation. ■ PPG Timer Operation PWM operation, one shot operation, interrupt source and timing are described next. FUJITSU MICROELECTRONICS LIMITED...
Page 369: Pwm Operation
CHAPTER 12 PPG TIMER 12.5 PPG Timer Operation MB90930 Series 12.5.1 PWM Operation In PWM operation, pulses can be output continuously after an activation trigger was detected. The cycle of the output pulse can be controlled by changing the PCSR value, the duty ratio can be controlled by changing the PDUT value.
Page 370 CHAPTER 12 PPG TIMER 12.5 PPG Timer Operation MB90930 Series Note: After writing data into PCSR, be sure to write to PDUT. Refer to the data sheet for the minimum pulse width of the external TRG input. However, even if a pulse with a smaller pulse width than quoted above is input, it may be recognized as valid.
Page 371: One Shot Operation
CHAPTER 12 PPG TIMER 12.5 PPG Timer Operation MB90930 Series 12.5.2 One Shot Operation In one shot operation, a single pulse with an arbitrary width can be output by a trigger. When restart is enabled, the counter value is reloaded if an activation trigger is detected during operation.
Page 372: Interrupt Source And Timing
CHAPTER 12 PPG TIMER 12.5 PPG Timer Operation MB90930 Series 12.5.3 Interrupt Source and Timing 2.5T (T: count clock cycle) is required at most for loading the count value after an activation trigger. Figure 12.5-5 Interrupt Output Sources and Timing Activation trigger →...
Page 373: Chapter 13 Real-Time Watch Timer
CHAPTER 13 REAL-TIME WATCH TIMER This chapter describes the functions and operations of the real-time watch timer. 13.1 Overview of Real-Time Watch Timer 13.2 Registers of Real-Time Watch Timer 13.3 Interrupts of Real-Time Watch Timer CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 374: Overview Of Real-Time Watch Timer
CHAPTER 13 REAL-TIME WATCH TIMER 13.1 Overview of Real-Time Watch Timer MB90930 Series 13.1 Overview of Real-Time Watch Timer The real-time watch timer consists of the real-time watch timer control register, sub-second data register, second/minute/hour/day data registers, 1/2 clock divider, 22-bit prescaler, and second/minute/hour/day counters. An MCU oscillation frequency of 4 MHz is used to operate the real-time watch timer specified.
Page 375: Registers Of Real-Time Watch Timer
CHAPTER 13 REAL-TIME WATCH TIMER 13.2 Registers of Real-Time Watch Timer MB90930 Series 13.2 Registers of Real-Time Watch Timer The six types of registers of the real-time watch timer are as follows: • Real-time watch timer control register (WTCR) • Sub-second data register (WTBR) •...
Page 376 CHAPTER 13 REAL-TIME WATCH TIMER 13.2 Registers of Real-Time Watch Timer MB90930 Series Figure 13.2-1 Registers of Real-Time Watch Timer Real-time watch timer Upper bits of control register Address : 0000CE Reserved Reserved INTE4 INT4 WTCRH (R/W) (R/W) (R/W) (R/W)
Page 377: Real-Time Watch Timer Control Register
CHAPTER 13 REAL-TIME WATCH TIMER 13.2 Registers of Real-Time Watch Timer MB90930 Series 13.2.1 Real-Time Watch Timer Control Register The real-time watch timer control register is used to start and stop the real-time watch timer, control interrupts, and set external output pins.
Page 378 CHAPTER 13 REAL-TIME WATCH TIMER 13.2 Registers of Real-Time Watch Timer MB90930 Series WTCRL [bit4] Undefined bits • If this bit is read, "1" is read. • Writing to this bit does not affect the operation. WTCRL [bit3, bit2, bit1] Reserved This bit must be set to "000".
Page 379: 13.2.2 Sub-Second Data Register
CHAPTER 13 REAL-TIME WATCH TIMER 13.2 Registers of Real-Time Watch Timer MB90930 Series 13.2.2 Sub-Second Data Register The sub-second data register stores the reload values of the 22-bit prescaler used for dividing the frequency of the oscillation clock. Reload values are specified in such a way that 22-bit prescaler output takes an interval of precisely half seconds.
Page 380: Second/Minute/Hour/Day Data Registers
CHAPTER 13 REAL-TIME WATCH TIMER 13.2 Registers of Real-Time Watch Timer MB90930 Series 13.2.3 Second/Minute/Hour/Day Data Registers The second/minute/hour/day data registers are used to store time information. The data of second, minute, hour, and day is indicated in binary notation. When these registers are read, the unit simply returns the counter values.
Page 381 CHAPTER 13 REAL-TIME WATCH TIMER 13.2 Registers of Real-Time Watch Timer MB90930 Series Note: Do not set impossible data (e.g., 60 seconds) in the WTSR, WTMR, WTHR, or WTDR register. Do not set the N4 to N1 bits to a value that conflicts with the value set in the MS1 and MS0 bits.
Page 382: Interrupts Of Real-Time Watch Timer
CHAPTER 13 REAL-TIME WATCH TIMER 13.3 Interrupts of Real-Time Watch Timer MB90930 Series 13.3 Interrupts of Real-Time Watch Timer The real-time watch timer can be generated an interrupt request when the sub- second counter, second counter, minute counter, hour counter, or day counter overflows.
Page 383: Chapter 14 Delay Interrupt Generation Module
CHAPTER 14 DELAY INTERRUPT GENERATION MODULE This chapter describes the functions and operations of the delay interrupt generation module. 14.1 Overview of Delay Interrupt Generation Module 14.2 Operation of Delay Interrupt Generation Module CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 384: Overview Of Delay Interrupt Generation Module
CHAPTER 14 DELAY INTERRUPT GENERATION MODULE 14.1 Overview of Delay Interrupt Generation Module MB90930 Series 14.1 Overview of Delay Interrupt Generation Module The delay interrupt generation module is used to generate an interrupt for task switching. Using this module enables software to issue/cancel an interrupt request to F MC-16LX CPU.
Page 385: Operation Of Delay Interrupt Generation Module
CHAPTER 14 DELAY INTERRUPT GENERATION MODULE 14.2 Operation of Delay Interrupt Generation Module MB90930 Series 14.2 Operation of Delay Interrupt Generation Module When the CPU writes "1" to the relevant bit in DIRR by software, the request latch in the delay interrupt generation module is set to generate an interrupt request to the interrupt controller.
Page 386 CHAPTER 14 DELAY INTERRUPT GENERATION MODULE 14.2 Operation of Delay Interrupt Generation Module MB90930 Series FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 387: Chapter 15 Dtp/External Interrupt Circuit
15.2 Configuration of DTP/External Interrupt Circuit 15.3 Pins of DTP/External Interrupt Circuit 15.4 Registers of DTP/External Interrupt Circuit 15.5 Operations of DTP/External Interrupt Circuit 15.6 Notes on Using the DTP/External Interrupt Circuit 15.7 Sample Programs of DTP/External Interrupt Circuit CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 388: Overview Of Dtp/External Interrupt Circuit
CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT 15.1 Overview of DTP/External Interrupt Circuit MB90930 Series 15.1 Overview of DTP/External Interrupt Circuit The DTP (Data Transfer Peripheral)/external interrupt circuit is located between externally connected peripheral units and the F MC-16LX CPU. This circuit is...
Page 389 CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT 15.1 Overview of DTP/External Interrupt Circuit MB90930 Series ■ Interrupts of DTP/External Interrupt Circuit and EI Table 15.1-2 lists interrupts of the DTP/external interrupt circuit and the EI Table 15.1-2 Interrupts of DTP/External Interrupt Circuit and EI...
Page 390: Configuration Of Dtp/External Interrupt Circuit
CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT 15.2 Configuration of DTP/External Interrupt Circuit MB90930 Series 15.2 Configuration of DTP/External Interrupt Circuit The DTP/external interrupt circuit consists of the following four blocks. • DTP/Interrupt input detection circuit • External interrupt level setting register (ELVRL/ELVRH) •...
Page 391 CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT 15.2 Configuration of DTP/External Interrupt Circuit MB90930 Series ● DTP/external interrupt input detection circuit When the level or edge selected for each pin by the external interrupt level setting register (ELVRH/ELVRL) is detected from a pin input signal and then the valid signal is detected. The IR bit of the external interrupt source register (EIRR) corresponding to the pin is set to "1".
Page 392: Pins Of Dtp/External Interrupt Circuit
CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT 15.3 Pins of DTP/External Interrupt Circuit MB90930 Series 15.3 Pins of DTP/External Interrupt Circuit This section describes the pins of the DTP/external interrupt circuit and their block diagram. ■ Pins of DTP/External Interrupt Circuit The pins of the DTP/external interrupt circuit are used as both general-purpose ports and other peripheral functions.
Page 393: Registers Of Dtp/External Interrupt Circuit
CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT 15.4 Registers of DTP/External Interrupt Circuit MB90930 Series 15.4 Registers of DTP/External Interrupt Circuit This section lists the registers of the DTP/external interrupt circuit. ■ Registers of DTP/External Interrupt Circuit The DTP/external interrupt circuit consists of the following three types.
Page 394: External Interrupt Source Register (Eirr)
CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT 15.4 Registers of DTP/External Interrupt Circuit MB90930 Series 15.4.1 External Interrupt Source Register (EIRR) The external interrupt source register (EIRR) is used to retain and clear interrupt sources. ■ External Interrupt Source Register (EIRR) Figure 15.4-2 shows the configuration of the external interrupt source register. Table 15.4-1 lists the functions of each bit.
Page 395: External Interrupt Enable Register (Enir)
CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT 15.4 Registers of DTP/External Interrupt Circuit MB90930 Series 15.4.2 External Interrupt Enable Register (ENIR) The external interrupt enable register (ENIR) is used to enable/disable interrupt request output to the CPU. ■ External Interrupt Enable Register (ENIR) Figure 15.4-3 shows the configuration of the external interrupt enable register (ENIR).
Page 396: External Interrupt Level Setting Register (Elvrh/Elvrl)
CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT 15.4 Registers of DTP/External Interrupt Circuit MB90930 Series 15.4.3 External Interrupt Level Setting Register (ELVRH/ELVRL) The external interrupt level setting register (ELVRH/ELVRL) is used to select a signal level or edge type for each pin for detecting that an signal input to the DTP/external interrupt pin is a DTP/external interrupt source.
Page 397: Operations Of Dtp/External Interrupt Circuit
CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT 15.5 Operations of DTP/External Interrupt Circuit MB90930 Series 15.5 Operations of DTP/External Interrupt Circuit The DTP/external interrupt circuit has an external interrupt function and a DTP function. This section describes the settings and operations of each function.
Page 398 CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT 15.5 Operations of DTP/External Interrupt Circuit MB90930 Series ● Switching between external interrupt function and DTP function To switch between the external interrupt function and the DTP function, set the ISE bit of the corresponding interrupt control register (ICR). When the ISE bit is "1", the extended intelligent service (EI OS) is enabled and the DTP function operates.
Page 399 CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT 15.5 Operations of DTP/External Interrupt Circuit MB90930 Series Figure 15.5-2 Flowchart of DTP/External Internal Circuit Operation DTP/External interrupt circuit Other request Interrupt controller ELVRH/ ELVRL EIRR Interrupt handling microprogram ENIR Source DTP processing routine OS starts)
Page 400: External Interrupt Function
CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT 15.5 Operations of DTP/External Interrupt Circuit MB90930 Series 15.5.1 External Interrupt Function The DTP/external interrupt circuit has an external interrupt function that issues an interrupt request by an input to the DTP external interrupt pin with a signal level selected.
Page 401: Dtp Function
CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT 15.5 Operations of DTP/External Interrupt Circuit MB90930 Series 15.5.2 DTP Function The DTP/external interrupt circuit has a DTP function that detects a signal from the external peripheral unit at the DTP/external interrupt pin to start an extended intelligent I/O service (EI OS).
Page 402: Notes On Using The Dtp/External Interrupt Circuit
CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT 15.6 Notes on Using the DTP/External Interrupt Circuit MB90930 Series 15.6 Notes on Using the DTP/External Interrupt Circuit This section provides notes on the signals input to the DTP/external interrupt circuit, and explains how to clear standby mode and interrupts.
Page 403 CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT 15.6 Notes on Using the DTP/External Interrupt Circuit MB90930 Series ● Notes on interrupts When the external interrupt function is active and the interrupt request output is enabled with the request flag bit "1", the process cannot return from the interrupt handling. Be sure to clear the external interrupt request flag bit in the interrupt handing routine.
Page 404: Sample Programs Of Dtp/External Interrupt Circuit
CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT 15.7 Sample Programs of DTP/External Interrupt Circuit MB90930 Series 15.7 Sample Programs of DTP/External Interrupt Circuit This section provides sample programs of the external interrupt function and the DTP function. ■ Sample Program of External Interrupt Function ●...
Page 405 CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT 15.7 Sample Programs of DTP/External Interrupt Circuit MB90930 Series RETI ; Return from interrupt. CODE ENDS ;----------Vector setting-------------------------------------- VECT CSEG ABS=0FFH 0FFBCH ; Set a vector for the interrupt ; #16 (10 WARI 0FFDCH ; Reset vector setting START ;...
Page 406 CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT 15.7 Sample Programs of DTP/External Interrupt Circuit MB90930 Series CCR, #0BFH ;Interrupt disabled I:ICR02, #08H ; Interrupt level 0 (highest) ; EI OS enable, ch.0 BAPL, #00H ; Set output data address BAPM, #06H BAPH, #00H ISCS, #12H ;...
Page 407: Chapter 16 8-/10-Bit A/D Converter
16.1 Overview of 8-/10-bit A/D Converter 16.2 Block Diagram of 8-/10-bit A/D Converter 16.3 Configuration of 8-/10-bit A/D Converter 16.4 Interrupts of 8-/10-bit A/D Converter 16.5 Explanation of 8-/10-bit A/D Converter Operations 16.6 Precautions when Using 8-/10-bit A/D Converter CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 408: Overview Of 8-/10-Bit A/D Converter
CHAPTER 16 8-/10-BIT A/D CONVERTER 16.1 Overview of 8-/10-bit A/D Converter MB90930 Series 16.1 Overview of 8-/10-bit A/D Converter The 8-/10-bit A/D converter converts analog input voltages to 8-bit or 10-bit digital values in the RC successive approximation conversion method.
Page 409 CHAPTER 16 8-/10-BIT A/D CONVERTER 16.1 Overview of 8-/10-bit A/D Converter MB90930 Series ■ Conversion Modes of 8-/10-bit A/D Converter The 8-/10-bit A/D converter has the following conversion modes: Table 16.1-1 Conversion Modes of 8-/10-bit A/D Converter Conversion mode Description...
Page 410: Block Diagram Of 8-/10-Bit A/D Converter
CHAPTER 16 8-/10-BIT A/D CONVERTER 16.2 Block Diagram of 8-/10-bit A/D Converter MB90930 Series 16.2 Block Diagram of 8-/10-bit A/D Converter The 8-/10-bit A/D converter consists of the following blocks. ■ Block Diagram of 8-/10-bit A/D Converter Figure 16.2-1 Block Diagram of 8-/10-bit A/D Converter...
Page 411 CHAPTER 16 8-/10-BIT A/D CONVERTER 16.2 Block Diagram of 8-/10-bit A/D Converter MB90930 Series ● Detailed descriptions of pins and other items in the block diagram Table 16.2-1 lists the actual pin names and interrupt request numbers of the 8-/10-bit A/D converter.
Page 412 CHAPTER 16 8-/10-BIT A/D CONVERTER 16.2 Block Diagram of 8-/10-bit A/D Converter MB90930 Series ● Decoder The decoder selects an analog input pin to be used for A/D conversion from the setting of the A/D conversion start channel select bits (ADSR: ANS4 to ANS0) and A/D conversion end channel select bits (ADSR: ANE4 to ANE0) in the A/D setting register.
Page 413: Configuration Of 8-/10-Bit A/D Converter
CHAPTER 16 8-/10-BIT A/D CONVERTER 16.3 Configuration of 8-/10-bit A/D Converter MB90930 Series 16.3 Configuration of 8-/10-bit A/D Converter The pins, registers and interrupt sources of the A/D converter are shown below. ■ Pins of 8-/10-bit A/D Converter The pins of the 8-/10-bit A/D converter are also used as general-purpose I/O ports. Table 16.3- 1 lists the functions of each pin and settings for when using the 8-/10-bit A/D converter.
Page 414 CHAPTER 16 8-/10-BIT A/D CONVERTER 16.3 Configuration of 8-/10-bit A/D Converter MB90930 Series Table 16.3-1 Pins of 8-/10-bit A/D Converter (2 / 2) Function Setting for when using 8-/10-bit Pin name Pin function name A/D converter P70/PWM1P0/ ch.8 P71/PWM1M0/ ch.9 P72/PWM2P0/ ch.10...
Page 415 CHAPTER 16 8-/10-BIT A/D CONVERTER 16.3 Configuration of 8-/10-bit A/D Converter MB90930 Series ■ List of Registers and Initial Values of 8-/10-bit A/D Converter Figure 16.3-1 List of Registers and Initial Values of 8-/10-bit A/D Converter CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 416: Upper Bits In The A/D Control Status Register (Adcs1)
CHAPTER 16 8-/10-BIT A/D CONVERTER 16.3 Configuration of 8-/10-bit A/D Converter MB90930 Series 16.3.1 Upper bits in the A/D control status register (ADCS1) The upper bits in the A/D control status register (ADCS1) enable the following settings: • Starting A/D conversion by software •...
Page 417 CHAPTER 16 8-/10-BIT A/D CONVERTER 16.3 Configuration of 8-/10-bit A/D Converter MB90930 Series ■ Upper Bits in the A/D Control Status Register (ADCS1) Figure 16.3-2 Upper Bits in the A/D Control Status Register (ADCS1) Initial value Address − 000021 BUSY INT INTE PAUS STS1 STS0 STRT 0000000X −...
Page 418 CHAPTER 16 8-/10-BIT A/D CONVERTER 16.3 Configuration of 8-/10-bit A/D Converter MB90930 Series Table 16.3-2 Functions of Upper Bits in the A/D Control Status Register (ADCS1) (1 / 3) Bit name Function This bit forcibly terminates the 8-/10-bit A/D converter. When read, it indicates whether the 8-/10-bit A/D converter is running or stopped.
Page 419 CHAPTER 16 8-/10-BIT A/D CONVERTER 16.3 Configuration of 8-/10-bit A/D Converter MB90930 Series Table 16.3-2 Functions of Upper Bits in the A/D Control Status Register (ADCS1) (2 / 3) Bit name Function The PAUS bit indicates that the A/D conversion data protection function has been activated.
Page 420 CHAPTER 16 8-/10-BIT A/D CONVERTER 16.3 Configuration of 8-/10-bit A/D Converter MB90930 Series Table 16.3-2 Functions of Upper Bits in the A/D Control Status Register (ADCS1) (3 / 3) Bit name Function These bits select the type of triggers used to start the 8-/10-bit A/D converter (start trigger).
Page 421: Lower Bits In The A/D Control Status Register (Adcs0)
CHAPTER 16 8-/10-BIT A/D CONVERTER 16.3 Configuration of 8-/10-bit A/D Converter MB90930 Series 16.3.2 Lower Bits in the A/D Control Status Register (ADCS0) The lower bits in the A/D control status register enable the following settings: • Selecting the A/D conversion mode •...
Page 422 CHAPTER 16 8-/10-BIT A/D CONVERTER 16.3 Configuration of 8-/10-bit A/D Converter MB90930 Series Table 16.3-3 Functions of Lower Bits in the A/D Control Status Register (ADCS0) Bit name Function These bits set the A/D conversion mode. For detailed information about how to use each mode, see Section "16.5 Explanation of 8-/10-bit A/D Converter Operations".
Page 423: A/D Data Registers (Adcr0/Adcr1)
CHAPTER 16 8-/10-BIT A/D CONVERTER 16.3 Configuration of 8-/10-bit A/D Converter MB90930 Series 16.3.3 A/D Data Registers (ADCR0/ADCR1) A/D data registers (ADCR0/ADCR1) are used to record the digital values generated from the conversion results. While ADCR0 records the lower 8 bits of the conversion results, ADCR1 records the highest 2 bits.
Page 424: A/D Setting Registers (Adsr0/Adsr1)
CHAPTER 16 8-/10-BIT A/D CONVERTER 16.3 Configuration of 8-/10-bit A/D Converter MB90930 Series 16.3.4 A/D Setting Registers (ADSR0/ADSR1) The A/D setting registers (ADSR0/ADSR1) enable the following settings: • Setting A/D conversion times (sampling time and compare time) • Setting sampling channels (start channel and end channel) •...
Page 425 CHAPTER 16 8-/10-BIT A/D CONVERTER 16.3 Configuration of 8-/10-bit A/D Converter MB90930 Series Table 16.3-5 Functions of A/D Setting Registers (ADSR0/ADSR1) (1 / 2) Bit name Function These bits set the sampling time for A/D conversion. bit15 ST2, ST1, ST0: •...
Page 426 CHAPTER 16 8-/10-BIT A/D CONVERTER 16.3 Configuration of 8-/10-bit A/D Converter MB90930 Series Table 16.3-5 Functions of A/D Setting Registers (ADSR0/ADSR1) (2 / 2) Bit name Function These bits set the channel at which A/D conversion ends. Start channel < End channel:...
Page 427 CHAPTER 16 8-/10-BIT A/D CONVERTER 16.3 Configuration of 8-/10-bit A/D Converter MB90930 Series ■ Setup for Sampling Time (Bits ST2 to ST0) Table 16.3-6 Correlation between Bit ST2 to ST0 and Sampling Times Example setting Sampling time setting (φ: Internal operating frequency) φ...
Page 428: Analog Input Enable Registers (Ader6,7,8)
CHAPTER 16 8-/10-BIT A/D CONVERTER 16.3 Configuration of 8-/10-bit A/D Converter MB90930 Series 16.3.5 Analog Input Enable Registers (ADER6,7,8) These registers enable or disable the analog input pins used for the 8-/10-bit A/D converter. ■ Analog Input Enable Registers (ADER6,7,8) Figure 16.3-6 Analog Input Enable Registers (ADER6,7,8)
Page 429 CHAPTER 16 8-/10-BIT A/D CONVERTER 16.3 Configuration of 8-/10-bit A/D Converter MB90930 Series Notes: • To use t he r egister as an analog inp ut pin, wr ite "1" t o th e bit s in the analog inp ut enable register (ADER6, 7, 8) corresponding to the pin to be used in order to set it as analog input.
Page 430: Interrupts Of 8-/10-Bit A/D Converter
CHAPTER 16 8-/10-BIT A/D CONVERTER 16.4 Interrupts of 8-/10-bit A/D Converter MB90930 Series 16.4 Interrupts of 8-/10-bit A/D Converter In the 8-/10-bit A/D converter, an interrupt request is generated when the conversion results are stored in the A/D data register (ADCR) upon the completion of A/D conversion.
Page 431: Explanation Of 8-/10-Bit A/D Converter Operations
CHAPTER 16 8-/10-BIT A/D CONVERTER 16.5 Explanation of 8-/10-bit A/D Converter Operations MB90930 Series 16.5 Explanation of 8-/10-bit A/D Converter Operations The 8-/10-bit A/D converter performs A/D conversion operation in the following conversion modes. Each mode is specified by setting the A/D conversion mode select bits in the A/D control status register (ADCS: MD1, MD0): •...
Page 432 CHAPTER 16 8-/10-BIT A/D CONVERTER 16.5 Explanation of 8-/10-bit A/D Converter Operations MB90930 Series • The A/D conversion operation will stop when the A/D conversion for the end channel is completed. If a start trigger is entered while the conversion operation is still stopped, the conversion sequence will return to the analog input of the start channel to continue the A/D conversion.
Page 433: Single Conversion Mode
CHAPTER 16 8-/10-BIT A/D CONVERTER 16.5 Explanation of 8-/10-bit A/D Converter Operations MB90930 Series 16.5.1 Single Conversion Mode In single conversion mode, A/D conversion is performed sequentially from the start channel to the end channel. The A/D conversion operation will stop when the A/D conversion for the end channel is completed.
Page 434 CHAPTER 16 8-/10-BIT A/D CONVERTER 16.5 Explanation of 8-/10-bit A/D Converter Operations MB90930 Series ■ Operations and Applications of Single Conversion Mode • When a start trigger is entered, an A/D conversion starts from the channel set by the A/D conversion start channel select bits (ANS4 to ANS0), and continues through to the channel set by the A/D conversion end channel select bits (ANE4 to ANE0).
Page 435: Continuous Conversion Mode
CHAPTER 16 8-/10-BIT A/D CONVERTER 16.5 Explanation of 8-/10-bit A/D Converter Operations MB90930 Series 16.5.2 Continuous Conversion Mode In continuous conversion mode, A/D conversion is performed sequentially from the start channel to the end channel. When the A/D conversion for the end channel is completed, the conversion sequence returns to the start channel to continue the A/D conversion operation.
Page 436 CHAPTER 16 8-/10-BIT A/D CONVERTER 16.5 Explanation of 8-/10-bit A/D Converter Operations MB90930 Series ■ Operations and Applications of Continuous Conversion Mode • When a start trigger is entered, an A/D conversion starts from the channel set by the A/D conversion start channel select bits (ANS4 to ANS0), and continues through to the channel set by the A/D conversion end channel select bits (ANE4 to ANE0).
Page 437: Stop Conversion Mode
CHAPTER 16 8-/10-BIT A/D CONVERTER 16.5 Explanation of 8-/10-bit A/D Converter Operations MB90930 Series 16.5.3 Stop Conversion Mode In the stop conversion mode, A/D conversion is performed by repeatedly stopping and starting at each channel. The A/D conversion sequence returns to...
Page 438 CHAPTER 16 8-/10-BIT A/D CONVERTER 16.5 Explanation of 8-/10-bit A/D Converter Operations MB90930 Series • To force the termination of an A/D conversion, write "0" to the A/D conversion operation flag bit in the A/D control status register (ADCS: BUSY).
Page 439: Conversion Operation By Ei Os Function
CHAPTER 16 8-/10-BIT A/D CONVERTER 16.5 Explanation of 8-/10-bit A/D Converter Operations MB90930 Series 16.5.4 Conversion Operation by EI OS Function In the 8-/10-bit A/D converter, the EI OS function can be used to transfer the A/D conversion results to the memory.
Page 440: A/D Conversion Data Protection Function
CHAPTER 16 8-/10-BIT A/D CONVERTER 16.5 Explanation of 8-/10-bit A/D Converter Operations MB90930 Series 16.5.5 A/D Conversion Data Protection Function The data protection function is activated when A/D conversion is performed while the output of interrupt requests is enabled. ■ Explanation of A/D Conversion Data Protection Function in 8-/10-bit A/D...
Page 441 CHAPTER 16 8-/10-BIT A/D CONVERTER 16.5 Explanation of 8-/10-bit A/D Converter Operations MB90930 Series ● A/D conversion data protection function when reading the A/D conversion results by CPU • When the A/D conversion results are stored in the A/D data register (ADCR) after A/D conversion is performed on analog input, "1"...
Page 442 CHAPTER 16 8-/10-BIT A/D CONVERTER 16.5 Explanation of 8-/10-bit A/D Converter Operations MB90930 Series Notes: • Do not clear the interrupt request flag bit from CPU (ADCS: INT = 0), when the EI function is used to transfer the A/D conversion results to the memory, or the data in the A/D data register, which is being transferred, may be rewritten.
Page 443 CHAPTER 16 8-/10-BIT A/D CONVERTER 16.5 Explanation of 8-/10-bit A/D Converter Operations MB90930 Series ● Processing flow of A/D conversion data protection function when EI OS is used Figure 16.5-6 shows the processing flow of the A/D conversion data protection function when OS is used.
Page 444: Precautions When Using 8-/10-Bit A/D Converter
CHAPTER 16 8-/10-BIT A/D CONVERTER 16.6 Precautions when Using 8-/10-bit A/D Converter MB90930 Series 16.6 Precautions when Using 8-/10-bit A/D Converter Precautions must be taken for the following points when using the 8-/10-bit A/D converter. ■ Precautions When Using 8-/10-bit A/D Converter ●...
Page 445: Chapter 17 Lin-Uart
LIN-UART. 17.1 Overview of LIN-UART 17.2 Configuration of LIN-UART 17.3 Pins of LIN-UART 17.4 LIN-UART Registers 17.5 Interrupts of LIN-UART 17.6 LIN-UART Baud Rates 17.7 Operation of LIN-UART 17.8 Notes on Using LIN-UART CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 446: Overview Of Lin-Uart
CHAPTER 17 LIN-UART 17.1 Overview of LIN-UART MB90930 Series 17.1 Overview of LIN-UART The LIN (Local Interconnect Network)-UART is a general-purpose serial data communication interface for performing synchronous or asynchronous communication (start-stop synchronization) with external devices. LIN-UART provides bidirectional communication function (normal mode), master-slave communication function (multiprocessor mode in master/slave systems), and special features for LIN bus systems.
Page 447 CHAPTER 17 LIN-UART 17.1 Overview of LIN-UART MB90930 Series Table 17.1-1 Functions of LIN-UART (2 / 2) Function • Master device operation • Slave device operation • LIN synch break detection LIN bus option • LIN synch break generation • Detection of start/stop edges in LIN synch field connected to input capture 0,...
Page 448 CHAPTER 17 LIN-UART 17.1 Overview of LIN-UART MB90930 Series Notes: • Mode 1 o peration is sup ported both for master and slave operation of LIN-UART in a master/slave connection system. • In Mo de 3, t he L IN-UART f unction is fixed t o the communication format 8N1-Format, LSB first.
Page 449: Configuration Of Lin-Uart
CHAPTER 17 LIN-UART 17.2 Configuration of LIN-UART MB90930 Series 17.2 Configuration of LIN-UART This section briefly outlines the blocks of the LIN-UART. ■ LIN-UART Consists of the Following Blocks • Reload counter • Reception control circuit • Reception shift register •...
Page 450 CHAPTER 17 LIN-UART 17.2 Configuration of LIN-UART MB90930 Series ■ Block Diagram of LIN-UART Figure 17.2-1 Block Diagram of LIN-UART OTO, ORE FRE EXT, REST Transmission clock Programming Reload Reception clock LBIE Transmission generation counter control circuit circuit Reception SCKn...
Page 451 CHAPTER 17 LIN-UART 17.2 Configuration of LIN-UART MB90930 Series ■ Explanation of the Blocks ● Reload counter 15-bit reload counter that functions as the dedicated baud rate generator. The reload counter consists of a 15-bit register for the reload value. It generates the transmitting and receiving clocks with the external clock or the internal clock.
Page 452 CHAPTER 17 LIN-UART 17.2 Configuration of LIN-UART MB90930 Series ● Oversampling circuit The oversampling circuit oversamples for five times in the asynchronous mode. The received value is determined by majority decision of sampling value. It is switched off in synchronous operation mode.
Page 453 CHAPTER 17 LIN-UART 17.2 Configuration of LIN-UART MB90930 Series ● Serial status register (SSR) Operating functions are as follows: • Indicating status of receive/transmit operations and errors • Specifying LSB first or MSB first as transfer direction • Receive interrupt enable/disable •...
Page 454: Pins Of Lin-Uart
CHAPTER 17 LIN-UART 17.3 Pins of LIN-UART MB90930 Series 17.3 Pins of LIN-UART This section lists and details the pins, interrupt sources, and registers of the LIN-UART. ■ Pins of LIN-UART The LIN-UART pins also serve as general-purpose ports. Table 17.3-1 lists the pin functions, I/ O formats, and settings required to use LIN-UART.
Page 455 CHAPTER 17 LIN-UART 17.3 Pins of LIN-UART MB90930 Series ■ Block Diagram of LIN-UART Pins Figure 17.3-1 Block Diagram of LIN-UART Pins Resource input Resource output Port data register (RDR) Resource output enable PDR read P-ch Output write PDR write...
Page 456: Lin-Uart Registers
CHAPTER 17 LIN-UART 17.4 LIN-UART Registers MB90930 Series 17.4 LIN-UART Registers This section lists LIN-UART registers. ■ List of LIN-UART Registers Figure 17.4-1 List of LIN-UART Registers • LIN-UART0 Address: bit15 bit8 bit7 bit0 000035 000034 SCR0 (serial control register)
Page 457: Serial Control Register (Scr)
CHAPTER 17 LIN-UART 17.4 LIN-UART Registers MB90930 Series 17.4.1 Serial Control Register (SCR) The serial control register (SCR) specifies parity, selects the stop bit and data lengths, selects a frame data format in mode 1, clears the reception error flag, and specifies whether to enable/disable transmission and reception.
Page 458 CHAPTER 17 LIN-UART 17.4 LIN-UART Registers MB90930 Series Table 17.4-1 Functions of Each Bit in Serial Control Register (SCR) Bit name Function This bit selects whether to add a parity bit (during transmission) and whether to detect parity (during reception).
Page 459: Lin-Uart Serial Mode Register (Smr)
CHAPTER 17 LIN-UART 17.4 LIN-UART Registers MB90930 Series 17.4.2 LIN-UART Serial Mode Register (SMR) LIN-UART serial mode register (SMR) selects an operation mode and baud rate clock and specifies whether to enable/disable output of serial data and clocks to the corresponding pin.
Page 460 CHAPTER 17 LIN-UART 17.4 LIN-UART Registers MB90930 Series Table 17.4-2 Functions of Each Bit in Serial Mode Register (SMR) Bit name Function MD1, MD0: bit7, Operation mode These two bits set the LIN-UART operation mode. bit6 setting bits This bit sets an external clock directly to the LIN-UART serial clock by OTO: writing "1".
Page 461: Serial Status Register (Ssr)
CHAPTER 17 LIN-UART 17.4 LIN-UART Registers MB90930 Series 17.4.3 Serial Status Register (SSR) The serial status register (SSR) checks the transmission and reception status and error status, and enables or disables the interrupts. ■ Serial Status Register (SSR) Figure 17.4-4 Serial Status Register (SSR)
Page 462 CHAPTER 17 LIN-UART 17.4 LIN-UART Registers MB90930 Series Table 17.4-3 Functions of Each Bit in Serial Status Register (SSR) Bit name Function • This bit is set to "1" when a parity error occurs during reception at PE=1 and is cleared when "1"...
Page 463: Reception Data Register And Transmission Data Register (Rdr/Tdr)
CHAPTER 17 LIN-UART 17.4 LIN-UART Registers MB90930 Series 17.4.4 Reception Data Register and Transmission Data Register (RDR/TDR) Both RDR and TDR registers are located at the same address. At reading, it functions as the reception data register. At writing, it functions as the transmission data register.
Page 464 CHAPTER 17 LIN-UART 17.4 LIN-UART Registers MB90930 Series ■ Transmission Data Register (TDR) Transmission data register (TDR) is the data buffer register for serial data transmission. When data to be transmitted is written to the transmission data register (TDR) in transmission enable state (SCR: TXE=1), it is transferred to the transmission shift register, then converted to serial data, and transmitted from the serial data output pin (SOTn pin).
Page 465: Extended Status Control Register (Escr)
CHAPTER 17 LIN-UART 17.4 LIN-UART Registers MB90930 Series 17.4.5 Extended Status Control Register (ESCR) Extended status control register (ESCR) provides several LIN functions (enabling/disabling LIN synch break interrupt, selecting LIN synch break length, and detecting LIN synch break), direct access to the SINn and SOTn pins and setting of continuous clock output in LIN-UART synchronous clock mode and sampling clock edge.
Page 466 CHAPTER 17 LIN-UART 17.4 LIN-UART Registers MB90930 Series Table 17.4-4 Functions in Each Bit of the Extended Status Control Register (ESCR) Bit name Function LBIE: This bit enables/disables LIN synch break detection interrupt. LIN synch break An interrupt is generated when the LIN synch break detected flag (LBD) is "1"...
Page 467: Extended Communication Control Register (Eccr)
CHAPTER 17 LIN-UART 17.4 LIN-UART Registers MB90930 Series 17.4.6 Extended Communication Control Register (ECCR) The extended communication control register (ECCR) provides bus idle detection, synchronous clock settings, and the LIN synch break generation. ■ Bit Configuration of Extended Communication Control Register (ECCR) Figure 17.4-7 shows the bit configuration of the extended communication control register...
Page 468 CHAPTER 17 LIN-UART 17.4 LIN-UART Registers MB90930 Series Table 17.4-6 Functions of Each Bit in the Extended Communication Control Register (ECCR) Bit name Function bit7 Unused bit This bit is unused. Read value is undefined. Always write "0" Writing "1" to this bit generates a LIN synch break of the length selected by the...
Page 469: Baud Rate Generator Registers 0 And 1 (Bgrn0/Bgrn1)
CHAPTER 17 LIN-UART 17.4 LIN-UART Registers MB90930 Series 17.4.7 Baud Rate Generator Registers 0 and 1 (BGRn0/ BGRn1) The baud rate generator registers 0 and 1 (BGRn0/BGRn1) set the division ratio for the clock value. Also, the count value of the transmission reload counter can be read.
Page 470: Interrupts Of Lin-Uart
CHAPTER 17 LIN-UART 17.5 Interrupts of LIN-UART MB90930 Series 17.5 Interrupts of LIN-UART LIN-UART uses both reception and transmission interrupts. An interrupt request can be generated for either of the following causes: • Receive data is set in the reception data register (RDR), or a reception error occurs.
Page 471 CHAPTER 17 LIN-UART 17.5 Interrupts of LIN-UART MB90930 Series ● Reception interrupt If one of the following events occurs in reception mode, the corresponding flag bit of the serial status register (SSR) is set to "1": Data reception is completed The received data was transferred from the serial input shift register to the reception data register (RDR) and data can be read (RDRF=1).
Page 472 CHAPTER 17 LIN-UART 17.5 Interrupts of LIN-UART MB90930 Series ● LIN synch field edge detection interrupts This works for LIN slave operation in operation mode 3. After LIN synch break detection, the internal signal is set to "1" at first falling edge of the LIN synch field and to the "0"...
Page 473: Timing Of Reception Interrupt Generation And Flag Set
CHAPTER 17 LIN-UART 17.5 Interrupts of LIN-UART MB90930 Series 17.5.1 Timing of Reception Interrupt Generation and Flag The following are the reception interrupt causes: completion of reception (SSR: RDRF) and occurrence of a reception error (SSR: PE, ORE, or FRE).
Page 474 CHAPTER 17 LIN-UART 17.5 Interrupts of LIN-UART MB90930 Series Figure 17.5-2 ORE Flag Set Timing Reception data RDRF FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 475: Timing Of Transmission Interrupt Generation And Flag Set
CHAPTER 17 LIN-UART 17.5 Interrupts of LIN-UART MB90930 Series 17.5.2 Timing of Transmission Interrupt Generation and Flag Set A transmission interrupt is generated when the transmission data is transferred from transmission data register (TDR) to transmission shift register and transmission is started.
Page 476 CHAPTER 17 LIN-UART 17.5 Interrupts of LIN-UART MB90930 Series ■ Transmission Interrupt Request Generation Timing If the TDRE flag is set to "1" when a transmission interrupt is enabled (SSR: TIE=1), transmission interrupt is generated. Note: A tr ansmission int errupt is g enerated im mediately after the tr ansmission int errupt is enabled (SSR:TIE=1) because the TDRE bit is set to "1"...
Page 477: Lin-Uart Baud Rates
CHAPTER 17 LIN-UART 17.6 LIN-UART Baud Rates MB90930 Series 17.6 LIN-UART Baud Rates One of the following can be selected for the LIN-UART transmission/reception clock source: • Dedicated baud rate generator (Reload Counter) • Input external clock to baud rate generator (Reload Counter) •...
Page 478 CHAPTER 17 LIN-UART 17.6 LIN-UART Baud Rates MB90930 Series Figure 17.6-1 Baud Rate Selection Circuit of LIN-UART REST Start bit falling edge detection Reload value: v Reception clock Rxc = 0? Reception Reload 15-bit reload counter Reset Rxc = v/2?
Page 479: Setting The Baud Rate
CHAPTER 17 LIN-UART 17.6 LIN-UART Baud Rates MB90930 Series 17.6.1 Setting the Baud Rate This section describes how the baud rates are set and the resulting serial clock frequency is calculated. ■ Calculating the Baud Rate The both 15-bit reload counters are programmed by the baud rate generator registers 1, 0 (BGRn1/BGRn0).
Page 480 CHAPTER 17 LIN-UART 17.6 LIN-UART Baud Rates MB90930 Series ■ Reload Value and Baud Rate for Each Clock Speed Reload value and baud rate for each clock speed is shown in Table 17.6-1. Table 17.6-1 Reload Value and Baud Rate...
Page 481 CHAPTER 17 LIN-UART 17.6 LIN-UART Baud Rates MB90930 Series Note: The e xternal cloc k signal is synchronized to the int ernal clock in th e LIN -UART. Th is means that indivisible external clock rates will result in phase unstable signals.
Page 482: Reload Counter
CHAPTER 17 LIN-UART 17.6 LIN-UART Baud Rates MB90930 Series 17.6.2 Reload counter The reload counter is a 15-bit reload counter that functions as dedicated baud rate generator. The transmission/reception clock is generated by the external or internal clock. The count value in the transmission reload counter can be read from the baud rate generator registers (BGR1, BGR0).
Page 483 CHAPTER 17 LIN-UART 17.6 LIN-UART Baud Rates MB90930 Series Figure 17.6-3 Example of a Simple Timer through Restarting the Reload Timer Clock Reload Counter Clock Outputs RESET Reload 35 100 99 Value Read BGR0/BGR1 Dat a : don’t care In this case, machine cycle after restart cyc is calculated as follows:...
Page 484: Operation Of Lin-Uart
CHAPTER 17 LIN-UART 17.7 Operation of LIN-UART MB90930 Series 17.7 Operation of LIN-UART LIN-UART operates in operation mode 0 for bidirectional serial communication, in mode 1 as master or slave in multiprocessor communication, and in mode 2 and 3 in bidirectional communication as master or slave.
Page 485 CHAPTER 17 LIN-UART 17.7 Operation of LIN-UART MB90930 Series ■ Synchronous Method In asynchronous operation, LIN-UART reception clock is automatically synchronized to the falling edge of a received start bit. In synchronous mode, the synchronization is performed either by the clock signal of the master device or by the clock signal if operating as master.
Page 486: Operation In Asynchronous Mode (Operation Modes 0 And 1)
CHAPTER 17 LIN-UART 17.7 Operation of LIN-UART MB90930 Series 17.7.1 Operation in Asynchronous Mode (Operation Modes 0 and 1) When LIN-UART is used in operation mode 0 (normal mode) or operation mode 1 (multiprocessor mode), the asynchronous transfer mode is selected.
Page 487 CHAPTER 17 LIN-UART 17.7 Operation of LIN-UART MB90930 Series Figure 17.7-1 Transmission/Reception Data Format (Operation Modes 0 and 1) [Operation mode 0] ST D0 D1 D2 D3 D4 D5 D6 D7 SP SP Without ST D0 D1 D2 D3 D4 D5 D6 D7 SP...
Page 488 CHAPTER 17 LIN-UART 17.7 Operation of LIN-UART MB90930 Series Note: As t he in itial v alue of transmission da ta empty flag bit (SS R: TD RE) is "1" if th e transmission interrupt is enabled (SSR: TIE=1), the interrupt occurs immediately.
Page 489 CHAPTER 17 LIN-UART 17.7 Operation of LIN-UART MB90930 Series ● Parity Parity can set to add (transmission) or detect (reception) the parity bit. The parity enable bit (SCR: PEN) specifies whether parity is enabled or disabled, and parity selection bit (SCR: P) selects the even/odd parity.
Page 490: Operation In Synchronous Mode (Operating Mode 2)
CHAPTER 17 LIN-UART 17.7 Operation of LIN-UART MB90930 Series 17.7.2 Operation in Synchronous Mode (Operating Mode 2) The clock synchronous transfer method is used for LIN-UART operation mode 2 (normal mode). ■ Operation in Synchronous Mode (Operation Mode 2) ●...
Page 491 CHAPTER 17 LIN-UART 17.7 Operation of LIN-UART MB90930 Series ● Clock supply In clock synchronous mode (normal), the number of the transmit/reception bits must be equal to the number of the clock cycles. When the start/stop bit is enabled, the number of the added start/stop bits must be equal, as well.
Page 492 CHAPTER 17 LIN-UART 17.7 Operation of LIN-UART MB90930 Series ● Communication settings for synchronous mode For communication in the synchronous mode, following settings have to be done: • Baud rate generator registers (BGR0/BGR1) Set the desired value for the dedicated baud rate reload counter.
Page 493: Operation With Lin Function (Operation Mode 3)
CHAPTER 17 LIN-UART 17.7 Operation of LIN-UART MB90930 Series 17.7.3 Operation with LIN Function (Operation Mode 3) LIN-UART can be used either as LIN-Master or LIN-Slave in operation mode 3. For this LIN function, setting the LIN-UART to mode 3 configures the data format to 8N1-LSB-first format.
Page 494 CHAPTER 17 LIN-UART 17.7 Operation of LIN-UART MB90930 Series Therefore, baud rate setting value is summarized as follows: without free-run timer overflow : BGR value = {(b-a) × Fe/(8 × φ)} -1 : BGR value = {(max + b-a) × Fe/(8 × φ)}-1...
Page 495 CHAPTER 17 LIN-UART 17.7 Operation of LIN-UART MB90930 Series Figure 17.7-8 UART Operation in LIN Slave Mode Serial Clock Serial input (LIN bus) LBR cleared by CPU ICU input (LSYN) Synch break (at 14-bit setting) Synch field ● LIN bus timing Figure 17.7-9 LIN Bus Timing and LIN-UART Signals...
Page 496: Serial Pin Direct Access
CHAPTER 17 LIN-UART 17.7 Operation of LIN-UART MB90930 Series 17.7.4 Serial Pin Direct Access LIN-UART allows the user to directly access to the transmission pin (SOTn) or the reception pin (SINn). ■ LIN-UART Pin Direct Access The LIN-UART provides the ability for the software to access directly to serial input or output pin.
Page 497: Bidirectional Communication Function (Normal Mode)
CHAPTER 17 LIN-UART 17.7 Operation of LIN-UART MB90930 Series 17.7.5 Bidirectional Communication Function (Normal Mode) In operation mode 0 or 2, normal serial bidirectional communication is available. Select operation mode 0 for asynchronous communication and operation mode 2 for synchronous communication.
Page 498 CHAPTER 17 LIN-UART 17.7 Operation of LIN-UART MB90930 Series ● Communication procedure Communication starts at arbitrary timing from the transmission side when the transmission data is provided. When the transmission data is received at the reception side, ANS (per one byte in example) is returned periodically.
Page 499: Master/Slave Type Communication Function (Multiprocessor Mode)
CHAPTER 17 LIN-UART 17.7 Operation of LIN-UART MB90930 Series 17.7.6 Master/Slave Type Communication Function (Multiprocessor Mode) LIN-UART communication with multiple CPUs connected in master/slave mode is available for both master or slave systems in the operation mode 1. ■ Master/Slave Type Communication Function Figure 17.7-13 shows the settings to operate LIN-UART in multiprocessor mode (operation...
Page 500 CHAPTER 17 LIN-UART 17.7 Operation of LIN-UART MB90930 Series ● Function selection Select the operation mode and data transfer mode for master-slave communication as shown in Table 17.7-3. Table 17.7-3 Selection of the Master/Slave Communication Function Operation mode Synchronous Data...
Page 501 CHAPTER 17 LIN-UART 17.7 Operation of LIN-UART MB90930 Series Figure 17.7-15 Master/Slave Communication Flowchart (Master CPU) (Slave CPU) Start Start Set to operation mode 1 Set to operation mode 1 Set the SINn pin as the serial Set the SINn pin as the serial...
Page 502: Lin Communication Function
CHAPTER 17 LIN-UART 17.7 Operation of LIN-UART MB90930 Series 17.7.7 LIN Communication Function LIN-UART communication with LIN devices is available for both LIN master or LIN slave systems. ■ LIN Master/Slave Type Communication Function The settings shown in Figure 17.7-16 are required to operate LIN-UART in LIN communication mode (operation mode 3).
Page 503: Sample Flowcharts For Lin-Uart In Lin Communication (Operation Mode 3)
CHAPTER 17 LIN-UART 17.7 Operation of LIN-UART MB90930 Series 17.7.8 Sample Flowcharts for LIN-UART in LIN Communication (Operation Mode 3) This section shows sample flowcharts for LIN-UART in LIN communication. ■ LIN Master Device Figure 17.7-18 LIN Master Flowchart Start...
Page 504 CHAPTER 17 LIN-UART 17.7 Operation of LIN-UART MB90930 Series ■ LIN Slave Device Figure 17.7-19 LIN Slave Flowchart Start Initial setting: Set to operation mode 3 Serial data output enabled TXE = 1, TIE = 0, RXE = 0, RIE = 1...
Page 505: Notes On Using Lin-Uart
CHAPTER 17 LIN-UART 17.8 Notes on Using LIN-UART MB90930 Series 17.8 Notes on Using LIN-UART Notes on using LIN-UART are given below. ■ Notes on Using LIN-UART ● Enabling operations The LIN-UART has the TXE (transmission) and RXE (reception) enable bit in the serial control register (SCR) for transmission and reception, respectively.
Page 506 CHAPTER 17 LIN-UART 17.8 Notes on Using LIN-UART MB90930 Series ● Software compatibility Although this LIN-UART is similar to the old FJ-UART, it is not software compatible to them. The programming models may be the same, but the structure of the registers differ.
Page 507: Chapter 18 Can Controller
18.7 Procedure of Transmission via Message Buffer (x) 18.8 Procedure of Reception Via Message Buffer (x) 18.9 Specifying the Multi-level Message Buffer Configuration 18.10 CAN WAKE UP Function 18.11 Precautions When Using CAN Controller 18.12 Sample Program of CAN CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 508: Features Of Can Controller
CHAPTER 18 CAN CONTROLLER 18.1 Features of CAN Controller MB90930 Series 18.1 Features of CAN Controller The CAN controller is a module that is integrated into a 16-bit microcomputer MC-16LX). CAN (Controller Area Network) is the standard protocol used for serial communication between controllers in automobiles, and is widely applied in the industrial fields.
Page 509: Block Diagram Of Can Controller
CHAPTER 18 CAN CONTROLLER 18.2 Block Diagram of CAN Controller MB90930 Series 18.2 Block Diagram of CAN Controller Figure 18.2-1 shows a block diagram of the CAN controller. ■ Block Diagram of CAN Controller Figure 18.2-1 Block Diagram of CAN Controller...
Page 510: Classification Of Can Controller Registers
CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series 18.3 Classification of CAN Controller Registers The CAN controller registers can be classified into the following 4 types: • General control register • Message buffer control register • Message buffer •...
Page 511 CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series ■ Message Buffer Control Registers The following 14 types of message buffer control registers are provided: • Message buffer valid register (BVALR) • IDE register (IDER) • Transmission request register (TREQR) •...
Page 512 CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series Table 18.3-2 List of Message Buffer Control Registers (2 / 2) Address Abbre- Register Access Initial Value viation CAN1 003D08 XXXXXXXX IDE register IDER (R/W) XXXXXXXX 003D09 003D0A...
Page 513 CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series ■ Message Buffers The following 3 types of message buffers are provided: • ID register x (x = 0 to 15) (IDRx) • DLC register x (x = 0 to 15) (DLCRx) •...
Page 514 CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series Table 18.3-3 List of Message Buffers (ID Register) (2 / 3) Address Abbre- Register Access Initial Value viation CAN1 003B34 XXXXXXXX XXXXXXXX 003B35 ID register 5 IDR5 (R/W)
Page 515 CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series Table 18.3-3 List of Message Buffers (ID Register) (3 / 3) Address Abbre- Register Access Initial Value viation CAN1 003B50 XXXXXXXX XXXXXXXX 003B51 ID register 12 IDR12 (R/W)
Page 516 CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series Table 18.3-4 List of Message Buffers (DLC Register) (1 / 2) Address Register Abbreviation Access Initial Value CAN1 003B60 ---- XXXX DLC register 0 DLCR0 (R/W) 003B61 003B62...
Page 517 CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series Table 18.3-4 List of Message Buffers (DLC Register) (2 / 2) Address Register Abbreviation Access Initial Value CAN1 003B7A ---- XXXX DLC register 13 DLCR13 (R/W) 003B7B 003B7C...
Page 518 CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series Table 18.3-5 List of Message Buffers (Data Register) Address Abbre- Register Access Initial Value viation CAN1 003B80 XXXXXXXX Data register 0 (8 bytes) DTR0 (R/W) 003B87 XXXXXXXX 003B88...
Page 519: Control Status Register (Csr)
CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series 18.3.1 Control Status Register (CSR) Bit operation instructions (read-modify-write instructions) cannot be used for the control status register (CSR). ■ Bit Configuration of Control Status Register (CSR) Figure 18.3-1 shows the bit configuration of the control status register (CSR).
Page 520 CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series When the node status transition interrupt enable bit (NIE) is "1", an interrupt is generated. Writing "0" to the NT bit sets the bit to "0". Writing "1" to this bit is ignored. "1" is read from this bit when a read-modify-write (RMW) instruction is executed.
Page 521 CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series [bit7] TOE: Transmission output enable bit Writing "1" to the TOE bit switches the general-purpose port pin to the CAN controller send pin. • 0: General-purpose port pin •...
Page 522 CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series ■ Bus Operation Stop Bit (HALT = 1) The bus operation stop bit sets or releases bus operation stop, or indicates the state of the bus operation. ●...
Page 523: Last Event Indication Register (Leir)
CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series 18.3.2 Last Event Indication Register (LEIR) The last event indication register (LEIR) indicates the last event. NTE, TCE and RCE are exclusive. When one of the last event bits is set to "1", other bits are set to "0".
Page 524 CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series [bit3 to bit0] MBP3 to MBP0: Message buffer pointer bits When the TCE or RCE bit is set to "1", the MBP3 to MBP0 bits indicate the number of the relevant message buffer (0 to 15).
Page 525: Receive And Transmit Error Counters (Rtec)
CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series 18.3.3 Receive and Transmit Error Counters (RTEC) The receive and transmit error counters (RTEC) indicate the transmit error count and receive error count defined by the CAN specifications.This register is read-only.
Page 526: Bit Timing Register (Btr)
CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series 18.3.4 Bit Timing Register (BTR) The bit timing register (BTR) sets the prescaler and bit timing. ■ Bit Configuration of Bit Timing Register (BTR) Figure 18.3-5 shows the bit configuration of the bit timing register (BTR).
Page 527 CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series Figure 18.3-6 Bit Time Segments in CAN Specifications Nominal bit time PROP_SEG PIUSL_SEG1 PIUSL_SEG2 SYNC_SEG Sample point Figure 18.3-7 Bit Time Segments in CAN Controller Nominal bit time...
Page 528 CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series ■ Sample Setting of the Bit Timing Register The following is the sample setting of the bit timing register. ● Operating conditions • Communication speed (BT): 100 kbps (10μs) •...
Page 529: Message Buffer Valid Register (Bvalr)
CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series 18.3.5 Message Buffer Valid Register (BVALR) The message buffer valid register (BVALR) sets the validity of message buffer (x) and indicates the state of the message buffer. ■ Bit Configuration of Message Buffer Valid Register (BVALR) Figure 18.3-8 shows the bit configuration of the message buffer valid register (BVALR).
Page 530: Ide Register (Ider)
CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series 18.3.6 IDE Register (IDER) The IDE register sets the frame format used by message buffer (x) during send/ receive operations. ■ Bit Configuration of IDE Register (IDER) Figure 18.3-9 shows the bit configuration of the IDE register (IDER).
Page 531: Transmission Request Register (Treqr)
CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series 18.3.7 Transmission Request Register (TREQR) The transmission request register (TREQR) sets a transmission request for message buffer (x) and indicate the state of the buffer. ■ Bit Configuration of Transmission Request Register (TREQR) Figure 18.3-10 shows the bit configuration of the transmission request register (TREQR).
Page 532: Transmission Rtr Register (Trtrr)
CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series 18.3.8 Transmission RTR register (TRTRR) The transmission RTR register (TRTRR) sets the transmission RTR (remote transmission request) bit via message buffer (x). ■ Bit Configuration of Transmission RTR Register (TRTRR) Figure 18.3-11 shows the bit configuration of the transmission RTR register (TRTRR).
Page 533: Remote Frame Receive Wait Register (Rfwtr)
CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series 18.3.9 Remote Frame Receive Wait Register (RFWTR) The remote frame receive wait register (RFWTR) sets the condition for starting transmission when a request for data frame transmission is set (TREQx in the transmission request register (TREQR) is "1"...
Page 534: Transmission Cancel Register (Tcanr)
CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series 18.3.10 Transmission Cancel Register (TCANR) The transmission cancel register (TCANR) cancels requests in wait state for transmission to message buffer (x) when "1" is written to TCANx. When canceling is completed, TREQx in the transmission request register (TREQR) becomes "0".
Page 535: Transmission Complete Register (Tcr)
CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series 18.3.11 Transmission Complete Register (TCR) When transmission via message buffer (x) is completed, the corresponding TCx becomes "1". When TIEx in the transmission interrupt enable register (TIER) is "1", an interrupt is generated.
Page 536: Transmission Interrupt Enable Register (Tier)
CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series 18.3.12 Transmission Interrupt Enable Register (TIER) The transmission interrupt enable register (TIER) enables or disables transmission interrupts via message buffer (x). A transmission interrupt is generated when transmission is completed (when TCx in the transmission complete register (TCR) becomes "1").
Page 537: Receive Complete Register (Rcr)
CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series 18.3.13 Receive Complete Register (RCR) When storing a receive message in message buffer (x) is completed, RCx becomes "1". When RIEx in the receive complete interrupt enable register is "1", an interrupt is generated.
Page 538: Remote Request Receive Register (Rrtrr)
CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series 18.3.14 Remote Request Receive Register (RRTRR) When a received remote frame is stored in message buffer (x), RRTRx becomes "1" (at the same time when the RCx setting becomes "1").
Page 539: Receive Overrun Register (Rovrr)
CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series 18.3.15 Receive Overrun Register (ROVRR) If the receive complete register (RCR) is already "1" when storing a receive message into message buffer (x) is completed, ROVRx becomes "1" to indicate that reception caused an overrun.
Page 540: Receive Interrupt Enable Register (Rier)
CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series 18.3.16 Receive Interrupt Enable Register (RIER) The receive interrupt enable register (RIER) enables or disables receive interrupts via message buffer (x). A receive interrupt is generated when reception is completed (when RCx in the receive complete register (RCR) is "1").
Page 541: Acceptance Mask Selection Register (Amsr)
CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series 18.3.17 Acceptance Mask Selection Register (AMSR) The acceptance mask selection register (AMSR) selects a mask (acceptance mask) for the comparison between the receive message ID and message buffer (x) ID.
Page 542 CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series Notes: • AMSx.1 and AMSx.0 must be set while message buffer (x) is invalid (when BVALx in the message buffer valid register (BVALR) is "0"). If these bits are set while the buffer is valid (BVALx = 1), unnecessary receive messages may be stored.
Page 543: Acceptance Mask Registers 0 And 1 (Amr0/Amr1)
CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series 18.3.18 Acceptance Mask Registers 0 and 1 (AMR0/AMR1) There are 2 types of acceptance mask register: AMR0 and AMR1, and both can be used in either the standard frame format or extended frame format.
Page 544 CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series (Continued) AMR1 BYTE2 Address: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 AM12 AM11 AM10 003D1A (CAN1) <- nitial value AMR1 BYTE3 Address: bit15 bit14 bit13 bit12 bit11...
Page 545: Message Buffers
CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series 18.3.19 Message Buffers There are 16 message buffers being provided, and 1 message buffer x (x = 0 to 15) consists of an ID register (IDRx), a DLC register (DLCRx), and a data register (DTRx).
Page 546: Id Register X (X = 0 To 15) (Idrx)
CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series 18.3.20 ID Register x (x = 0 to 15) (IDRx) ID register x (x = 0 to 15) (IDRx) is an ID register for message buffer (x). ■ Bit Configuration of ID Register x (x = 0 to 15) (IDRx) Figure 18.3-22 shows the bit configuration of ID register x (x = 0 to 15) (IDRx).
Page 547 CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series Notes: • Write operation to the ID register must be performed in units of words. Note that the write operation in units of bytes may result in undefined data being written to the upper byte during writing to the lower byte.
Page 548 CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series Table 18.3-8 Sample Setting of ID Register in Standard Frame Format (2 / 2) ID (Decimal) ID (Hexadecimal) BYTE0 BYTE1 • • • • 2043 2044 2045 2046 2047 Table 18.3-9 Sample Setting of ID Register in Extended Frame Format (1 / 2)
Page 549 CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series Table 18.3-9 Sample Setting of ID Register in Extended Frame Format (2 / 2) ID (Decimal) ID (Hexadecimal) BYTE0 BYTE1 BYTE0 BYTE1 • • • • 2043 2044...
Page 550: Dlc Register X (X = 0 To 15) (Dlcrx)
CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series 18.3.21 DLC Register x (x = 0 to 15) (DLCRx) DLC register x (x = 0 to 15) (DLCRx) stores DLC corresponding to message buffer x. ■ Bit Configuration of DLC Register x (x = 0 to 15) (DLCRx) Figure 18.3-23 shows the bit configuration of DLC register x (x = 0 to 15) (DLCRx).
Page 551: Data Register X (X = 0 To 15) (Dtrx)
CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series 18.3.22 Data Register x (x = 0 to 15) (DTRx) Data register x (x = 0 to 15) (DTRx) is a data register for message buffer (x). Data register x (x = 0 to 15) (DTRx) is used only to send or receive data frames;...
Page 552 CHAPTER 18 CAN CONTROLLER 18.3 Classification of CAN Controller Registers MB90930 Series (Continued) BYTE6 Address: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 003B86 +8x (CAN1) <- nitial alue BYTE7 Address: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 003B87 +8x (CAN1) <-...
Page 553: Can Controller Transmission
CHAPTER 18 CAN CONTROLLER 18.4 CAN Controller Transmission MB90930 Series 18.4 CAN Controller Transmission The CAN controller starts the transmission via message buffer (x) when "1" is written to TREQx in the transmission request register (TREQR). At this moment, TREQx becomes "1" and TCx in the transmission complete register (TCR) becomes "0".
Page 554 CHAPTER 18 CAN CONTROLLER 18.4 CAN Controller Transmission MB90930 Series ■ Flowchart of CAN Transmission Setting Figure 18.4-1 shows a flowchart of the CAN transmission setting. Figure 18.4-1 Flowchart of CAN Transmission Setting START Set bit timing: Bit timing register (BTR)
Page 555 CHAPTER 18 CAN CONTROLLER 18.4 CAN Controller Transmission MB90930 Series ■ Flowchart of CAN Controller Transmission Figure 18.4-2 shows a flowchart of the CAN controller transmission. Figure 18.4-2 Flowchart of CAN Controller Transmission Transmission request (TREQx = 1) TCx = 0...
Page 556: Can Controller Reception
CHAPTER 18 CAN CONTROLLER 18.5 CAN Controller Reception MB90930 Series 18.5 CAN Controller Reception Reception starts when the start of a data frame or a remote frame (SOF) is detected on the CAN bus. ■ Acceptance Filtering Receive messages in the standard frame format are compared with message buffer (x) set in the standard frame format (IDEx in the IDE register (IDER) is "0").
Page 557 CHAPTER 18 CAN CONTROLLER 18.5 CAN Controller Reception MB90930 Series Figure 18.5-1 Flowchart for Determining Message Buffer (x) which Stores Receive Messages Start Are message buffers with RCx set to "0" or with AMSx.1 and AMSx.0 set to "00 "...
Page 558 CHAPTER 18 CAN CONTROLLER 18.5 CAN Controller Reception MB90930 Series ■ Receive Complete RCx in the receive complete register (RCR) becomes "1" after a receive message is stored. When receive interrupts are enabled (RIEx in the receive interrupt enable register (RIER) is "1"), an interrupt is generated.
Page 559 CHAPTER 18 CAN CONTROLLER 18.5 CAN Controller Reception MB90930 Series ■ Flowchart of CAN Controller Reception Figure 18.5-3 shows a flowchart of the CAN controller reception. Figure 18.5-3 Flowchart of CAN Controller Reception Detect start of data frame or remote frame (SDF)
Page 560: Using Can Controller
CHAPTER 18 CAN CONTROLLER 18.6 Using CAN Controller MB90930 Series 18.6 Using CAN Controller Using the CAN controller requires the following settings: • Bit timing setting • Frame format setting • ID setting • Acceptance filter setting • Low-power consumption mode setting ■...
Page 561: Procedure Of Transmission Via Message Buffer (X)
CHAPTER 18 CAN CONTROLLER 18.7 Procedure of Transmission via Message Buffer (x) MB90930 Series 18.7 Procedure of Transmission via Message Buffer (x) After completing the settings of the bit timing, frame format, ID, and acceptance filter, set BVALx to "1" to validate message buffer (x).
Page 562 CHAPTER 18 CAN CONTROLLER 18.7 Procedure of Transmission via Message Buffer (x) MB90930 Series ● Setting a transmission request To make a transmission request, set TREQx in the transmission request register (TREQR) to "1". ● Clearing a transmission request To clear a transmission request to message buffer (x), write "1" to TCANx in the transmission cancel register (TCANR).
Page 563: Procedure Of Reception Via Message Buffer (X)
CHAPTER 18 CAN CONTROLLER 18.8 Procedure of Reception Via Message Buffer (x) MB90930 Series 18.8 Procedure of Reception Via Message Buffer (x) After completing the settings of the bit timing, frame format, ID, and acceptance filter, make the following settings.
Page 564 CHAPTER 18 CAN CONTROLLER 18.8 Procedure of Reception Via Message Buffer (x) MB90930 Series Figure 18.8-1 Example of Receive Interrupt Handling Interrupt when RCx = 1 Read receive message A := ROVRx ROVRx := 0 A = 0? RCx := 0...
Page 565: Specifying The Multi-Level Message Buffer Configuration
CHAPTER 18 CAN CONTROLLER 18.9 Specifying the Multi-level Message Buffer Configuration MB90930 Series 18.9 Specifying the Multi-level Message Buffer Configuration When the time to process messages is insufficient, such as when reception is performed frequently or an unspecified number of messages are received, combine more than one message buffer into a multi-level message buffer to provide the CPU with some time reserve for processing receive messages.
Page 566 CHAPTER 18 CAN CONTROLLER 18.9 Specifying the Multi-level Message Buffer Configuration MB90930 Series Figure 18.9-1 Example of Multi-level Message Buffer Operation : Initialized AMS15, AMS14, AMS13 AMSR 10 10 AM28 to AM18 AMR0 is selected 0000 1111 111 AMS0 ID28 to ID18...
Page 567: 18.10 Can Wake Up Function
CHAPTER 18 CAN CONTROLLER 18.10 CAN WAKE UP Function MB90930 Series 18.10 CAN WAKE UP Function The RX1 pin is shared with INT1 pin respectively. Enabling an interrupt by INT1 allows WAKE UP by a CAN receive operation. ■ Pins Used for CAN WAKE UP Function Since the RX1 pin is shared with the INT1 pin, enabling an interrupt by INT2 allows the use of the WAKE UP function.
Page 568: 18.11 Precautions When Using Can Controller
CHAPTER 18 CAN CONTROLLER 18.11 Precautions When Using CAN Controller MB90930 Series 18.11 Precautions When Using CAN Controller Using the CAN controller requires the following cautions. ■ Caution for Disabling Message Buffer by BVAL Bits When the BVAL bits are used to disable message buffers in order to read/write contents of the message buffer, the CAN controller may not perform send/receive operation properly.
Page 569: 18.12 Sample Program Of Can
CHAPTER 18 CAN CONTROLLER 18.12 Sample Program of CAN MB90930 Series 18.12 Sample Program of CAN This section shows a sample program of CAN. ■ Sample Program for CAN Transmission/Reception ● Processing specifications Set buffer 5 in CAN0 for data frame transmission, and buffer 0 for the reception.
Page 570 CHAPTER 18 CAN CONTROLLER 18.12 Sample Program of CAN MB90930 Series MOVW TREQR0, #0020H ; Transmission request register ; (1: transmission start, 0: ; transmission stop) //receive complete interrupt CAN0RX MOVW, #0000H ; Receive complete register RETI //transmission complete interrupt CAN0TX MOVW TREQR0, #0020H ;...
Page 571: Chapter 19 Lcd Controller/Driver
This chapter describes the functions and operations of the LCD controller/driver. 19.1 Overview of LCD Controller/Driver 19.2 Configuration of LCD Controller/Driver 19.3 LCD Controller/Driver Pins 19.4 Registers of LCD Controller/Driver 19.5 LCD Controller/Driver Display RAM 19.6 Operation of LCD Controller/Driver CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 572: Overview Of Lcd Controller/Driver
CHAPTER 19 LCD CONTROLLER/DRIVER 19.1 Overview of LCD Controller/Driver MB90930 Series 19.1 Overview of LCD Controller/Driver The LCD controller/driver has a built-in display data memory of 16 × 8 bits and controls the LCD display with 4 common outputs and 32 segment outputs.
Page 573: Configuration Of Lcd Controller/Driver
CHAPTER 19 LCD CONTROLLER/DRIVER 19.2 Configuration of LCD Controller/Driver MB90930 Series 19.2 Configuration of LCD Controller/Driver The LCD controller/driver contains the following 8 blocks. It functionally consists of two sections: the controller section where a segment and common signals are generated according to the contents of the display RAM, and the driver section, which drives the LCD.
Page 574 CHAPTER 19 LCD CONTROLLER/DRIVER 19.2 Configuration of LCD Controller/Driver MB90930 Series ● Lower bits in the LCD control register (LCRL) Performs LCD drive power control, and selects display/display blanking, display mode selection, and LCD clock interval selection. ● Upper bits in the LCD control register (LCRH) Switches between segment outputs (SEG12 to SEG23) and the general-purpose port.
Page 575: Internal Divided Resistor Of Lcd Controller/Driver
CHAPTER 19 LCD CONTROLLER/DRIVER 19.2 Configuration of LCD Controller/Driver MB90930 Series 19.2.1 Internal Divided Resistor of LCD Controller/Driver The LCD driver's power supply voltage is generated via an external divide resistor connected to pins V0 to V3 or an internal divide resistor.
Page 576 CHAPTER 19 LCD CONTROLLER/DRIVER 19.2 Configuration of LCD Controller/Driver MB90930 Series ■ Using the Internal Divided Resistor Even if the internal divide resistor is used, connect an external resistor between V and V3. Figure 19.2-3 shows a state when using the internal divide resistor.
Page 577: External Divided Resistor Of Lcd Controller/Driver
CHAPTER 19 LCD CONTROLLER/DRIVER 19.2 Configuration of LCD Controller/Driver MB90930 Series 19.2.2 External Divided Resistor of LCD Controller/Driver An external divide resistor or internal divide resistor is used to generate the LCD drive voltage. The brightness can be controlled by connecting a variable resistor between the and V3 pins.
Page 578 CHAPTER 19 LCD CONTROLLER/DRIVER 19.2 Configuration of LCD Controller/Driver MB90930 Series ■ Using the External Divide Resistor If an external divide resistor is used, the current that flows into the resistor when the LCD controller is stopped can be blocked by connecting the V...
Page 579: Lcd Controller/Driver Pins
CHAPTER 19 LCD CONTROLLER/DRIVER 19.3 LCD Controller/Driver Pins MB90930 Series 19.3 LCD Controller/Driver Pins The pins of the LCD controller/driver and their block diagram are shown in this section. ■ Pins of the LCD Controller/Driver The pins of the LCD controller/driver include 4 common output pins (COM0 to COM3), 32 segment output pins (SEG00 to SEG31), and 4 LCD drive power supply pins (V0 to V3).
Page 580 CHAPTER 19 LCD CONTROLLER/DRIVER 19.3 LCD Controller/Driver Pins MB90930 Series ■ Block Diagram of LCD Controller/Driver Pins Figure 19.3-1 shows a block diagram of multiplexed pins with segment output. Figure 19.3-1 Block Diagram of LCD Controller/Driver Pins Multi-use pins with segment output...
Page 581: Registers Of Lcd Controller/Driver
CHAPTER 19 LCD CONTROLLER/DRIVER 19.4 Registers of LCD Controller/Driver MB90930 Series 19.4 Registers of LCD Controller/Driver This section describes the registers of the LCD controller/driver. ■ Bit Configuration of LCD Controller/Driver Register Figure 19.4-1 shows the bit configuration of the registers of the LCD controller/driver.
Page 582: Lower Bits In The Lcd Control Register (Lcrl)
CHAPTER 19 LCD CONTROLLER/DRIVER 19.4 Registers of LCD Controller/Driver MB90930 Series 19.4.1 Lower Bits in the LCD Control Register (LCRL) The lower bits in the LCD control register (LCRL) are used to control the drive power, select display blanking, and select the display mode.
Page 583 CHAPTER 19 LCD CONTROLLER/DRIVER 19.4 Registers of LCD Controller/Driver MB90930 Series Table 19.4-1 Functions of Each Lower Bit in the LCD Control Register (LCRL) Bit name Function The selection bit for the frame interval generation clock. CSS: bit7 If this bit is set to "0", the time-base timer clock output is selected. If this bit is set Clock selection to "1", the sub clock is selected.
Page 584: Upper Bits In The Lcd Control Register (Lcrh)
CHAPTER 19 LCD CONTROLLER/DRIVER 19.4 Registers of LCD Controller/Driver MB90930 Series 19.4.2 Upper Bits in the LCD Control Register (LCRH) This register is used to select bias mode, switch between segment output (SEG12 to SEG23) and general-purpose port (P36, P37, P40 to P47, P90, P91).
Page 585 CHAPTER 19 LCD CONTROLLER/DRIVER 19.4 Registers of LCD Controller/Driver MB90930 Series Table 19.4-2 Functions of Each Upper Bit in the LCD Control Register (LCRH) Bit name Function Reserved: bit15 Be sure to set this bit to "0". Reserved bit SEG5:...
Page 586: Lcd Output Control Register 2/1 (Locr2/Locr1)
CHAPTER 19 LCD CONTROLLER/DRIVER 19.4 Registers of LCD Controller/Driver MB90930 Series 19.4.3 LCD Output Control Register 2/1 (LOCR2/LOCR1) These registers are used to switch between segment output (SEG00 to SEG11, SEG24 to SEG31) and general-purpose port (P22 to P27, P30 to P35, P00 to P07).
Page 587 CHAPTER 19 LCD CONTROLLER/DRIVER 19.4 Registers of LCD Controller/Driver MB90930 Series Table 19.4-3 Setting and Pin Functions of LCD Output Control Register 2/1 (LOCR2/LOCR1) (2 / 2) Segment output SEG31 to SEG24 SEG10_11 to SEG00 Segment output General-purpose port Initial value 00000001...
Page 588 CHAPTER 19 LCD CONTROLLER/DRIVER 19.4 Registers of LCD Controller/Driver MB90930 Series Table 19.4-5 Functions of Each Bit in the LCD Output Control Register 2 (LOCR2) Bit name Function SEG31: Switches whether to use the P07/SEG31 pin as the segment output or general-...
Page 589: Lcd Output Control Register 3 (Locr3)
CHAPTER 19 LCD CONTROLLER/DRIVER 19.4 Registers of LCD Controller/Driver MB90930 Series 19.4.4 LCD Output Control Register 3 (LOCR3) This register is used to switch between reference power supply pins (V0 to V2) and general-purpose port (P94 to P96) of the LCD controller/driver.
Page 590: Lcd Controller/Driver Display Ram
CHAPTER 19 LCD CONTROLLER/DRIVER 19.5 LCD Controller/Driver Display RAM MB90930 Series 19.5 LCD Controller/Driver Display RAM The display RAM is a 16 × 8 bits display data memory to generate a segment output signal. ■ Display RAM and Output Pins The RAM data is automatically read out in synchronization with the selected timing of the common signal and output from the segment output pin.
Page 591 CHAPTER 19 LCD CONTROLLER/DRIVER 19.5 LCD Controller/Driver Display RAM MB90930 Series Figure 19.5-1 Display RAM and Correspondence between Common Output Pins and Segment Output Pins Address COM3 COM2 COM1 COM0 bit3 bit2 bit1 bit0 SEG00 3960 bit7 bit6 bit5 bit4...
Page 592 CHAPTER 19 LCD CONTROLLER/DRIVER 19.5 LCD Controller/Driver Display RAM MB90930 Series Table 19.5-1 Relationship between Display RAM and Segment Output Pins, and Multiplexed Pins Value of SEG5 to SEG0 Pins used as Segment to output Display RAM area bits in the LCRH register...
Page 593 CHAPTER 19 LCD CONTROLLER/DRIVER 19.5 LCD Controller/Driver Display RAM MB90930 Series Table 19.5-3 Relationship between Duty, Common Output, and Bits Used as Display RAM Bits used for each display data Duty setting Common output value bit7 bit6 bit5 bit4 bit3...
Page 594: Operation Of Lcd Controller/Driver
CHAPTER 19 LCD CONTROLLER/DRIVER 19.6 Operation of LCD Controller/Driver MB90930 Series 19.6 Operation of LCD Controller/Driver The LCD controller/driver controls and drives the LCD display. ■ Operation of LCD Controller/Driver The settings shown in Figure 19.6-1 are required for the LCD display.
Page 595 CHAPTER 19 LCD CONTROLLER/DRIVER 19.6 Operation of LCD Controller/Driver MB90930 Series ■ Drive Waveform of the LCD If the LCD is driven with the DC, the LCD element, by its nature, undergoes a chemical change causing a deterioration of the element. Therefore, the LCD controller/driver has a built- in AC circuit to drive the LCD with a two-frame AC waveform.
Page 596: Output Waveform During The Lcd Controller/Driver Operation (1/2 Duty)
CHAPTER 19 LCD CONTROLLER/DRIVER 19.6 Operation of LCD Controller/Driver MB90930 Series 19.6.1 Output Waveform during the LCD Controller/Driver Operation (1/2 Duty) The display drive output is a 2-frame AC waveform of the multiplex drive method. Only COM0 and COM1 are used for display while 1/2 duty. COM2 and COM3 are not used.
Page 597 CHAPTER 19 LCD CONTROLLER/DRIVER 19.6 Operation of LCD Controller/Driver MB90930 Series Figure 19.6-2 Example of 1/2 Bias, 1/2 Duty Output Waveform COM0 COM1 COM2 COM3 SEGn SEG (n + 1) (ON) (ON) (ON) (ON) (ON) (ON) (ON) (ON) 1 frame...
Page 598 CHAPTER 19 LCD CONTROLLER/DRIVER 19.6 Operation of LCD Controller/Driver MB90930 Series ■ Example of LCD Panel Connection and Display Data (1/2 Duty Drive Method) Figure 19.6-3 Example of LCD Panel Display Data e.g.) Whendisplaying 5 SEGn SEG(n + 3) COM1...
Page 599: Output Waveform During The Lcd Controller/Driver Operation (1/3 Duty)
CHAPTER 19 LCD CONTROLLER/DRIVER 19.6 Operation of LCD Controller/Driver MB90930 Series 19.6.2 Output Waveform during the LCD Controller/Driver Operation (1/3 Duty) COM0, COM1, and COM2 are used for display while 1/3 duty. COM3 is not used. ■ 1/3 Bias, 1/3 Duty Output Waveform The LCD element is turned ON for which the potential difference between the common output and segment output is greatest.
Page 600 CHAPTER 19 LCD CONTROLLER/DRIVER 19.6 Operation of LCD Controller/Driver MB90930 Series Figure 19.6-4 Example of 1/3 Bias, 1/3 Duty Output Waveform COM0 COM1 COM2 COM3 SEGn SEG (n + 1) 3 (ON) 3 (ON) 3 (ON) 3 (ON) 3 (ON)
Page 601 CHAPTER 19 LCD CONTROLLER/DRIVER 19.6 Operation of LCD Controller/Driver MB90930 Series ■ Example of LCD Panel Connection and Display Data (1/3 Duty Drive Method) Figure 19.6-5 Example of LCD Panel Display Data e.g.)When displa ying 5 COM0 COM1 SEGn COM3...
Page 602: Output Waveform During The Lcd Controller/Driver Operation (1/4 Duty)
CHAPTER 19 LCD CONTROLLER/DRIVER 19.6 Operation of LCD Controller/Driver MB90930 Series 19.6.3 Output Waveform during the LCD Controller/Driver Operation (1/4 Duty) COM0, COM1, COM2, and COM3 are all used for display while 1/4 duty. ■ 1/3 Bias, 1/4 Duty Output Waveform The LCD element is turned ON for which the potential difference between the common output and segment output is greatest.
Page 603 CHAPTER 19 LCD CONTROLLER/DRIVER 19.6 Operation of LCD Controller/Driver MB90930 Series Figure 19.6-6 Example of 1/3 Bias, 1/4 Duty Output Waveform COM0 COM1 COM2 COM3 SEGn SEG (n + 1) 3 (ON) 3 (ON) 3 (ON) 3 (ON) 3 (ON)
Page 604 CHAPTER 19 LCD CONTROLLER/DRIVER 19.6 Operation of LCD Controller/Driver MB90930 Series ■ Example of LCD Panel Connection and Display Data (1/4 Duty Drive Method) Figure 19.6-7 Example of LCD Panel Display Data e.g.)When displa ying 5 COM3 COM0 SEGn COM1...
Page 605: Chapter 20 Low-Voltage/Cpu Operation Detection Reset Circuit
20.3 Register of the Low-voltage/CPU Operation Detection Reset Circuit 20.4 Operation of the Low-voltage/CPU Operation Detection Reset Circuit 20.5 Notes on Using the Low-voltage/CPU Operation Detection Reset Circuit 20.6 Sample Program for the Low-voltage/CPU Operation Detection Reset Circuit CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 606: Overview Of The Low-Voltage/Cpu Operation Detection Reset
CHAPTER 20 LOW-VOLTAGE/CPU OPERATION DETECTION RESET CIRCUIT 20.1 Overview of the Low-voltage/CPU Operation Detection MB90930 Series Reset 20.1 Overview of the Low-voltage/CPU Operation Detection Reset The low-voltage detection reset circuit has the function to monitor the supply voltage and detect the voltage drop. If it detects a low voltage, an internal reset is generated.
Page 607 CHAPTER 20 LOW-VOLTAGE/CPU OPERATION DETECTION RESET CIRCUIT 20.1 Overview of the Low-voltage/CPU Operation Detection MB90930 Series Reset ■ CPU Operation Detection Reset Circuit The CPU operation detection reset circuit is a counter to prevent the program from running out of control. This circuit starts automatically after the power is turned on. Once started, the counter of the circuit must be cleared regularly within a specified time.
Page 608: Configuration Of The Low-Voltage/Cpu Operation Detection
CHAPTER 20 LOW-VOLTAGE/CPU OPERATION DETECTION RESET CIRCUIT 20.2 Configuration of the Low-Voltage/CPU Operation Detection MB90930 Series 20.2 Configuration of the Low-Voltage/CPU Operation Detection The low-voltage/CPU operation detection reset circuit consists of 3 blocks: • CPU operation detection circuit • Voltage compare circuit •...
Page 609 CHAPTER 20 LOW-VOLTAGE/CPU OPERATION DETECTION RESET CIRCUIT 20.2 Configuration of the Low-Voltage/CPU Operation Detection MB90930 Series ● CPU operation detection circuit A counter used to prevent the program from running out of control. Once started, the counter of the circuit must be cleared regularly within a specified time.
Page 610: Register Of The Low-Voltage/Cpu Operation Detection Reset Circuit
CHAPTER 20 LOW-VOLTAGE/CPU OPERATION DETECTION RESET CIRCUIT 20.3 Register of the Low-voltage/CPU Operation Detection MB90930 Series Reset Circuit 20.3 Register of the Low-voltage/CPU Operation Detection Reset Circuit The low-voltage/CPU operation detection reset control register (LVRC) clears the counters of the low-voltage/CPU operation detection reset flag and the CPU operation detection circuit.
Page 611 CHAPTER 20 LOW-VOLTAGE/CPU OPERATION DETECTION RESET CIRCUIT 20.3 Register of the Low-voltage/CPU Operation Detection MB90930 Series Reset Circuit Table 20.3-1 Functions of Each Bit in the Low-voltage/CPU Operation Detection Reset Control Register Bit name Function bit7, Reserved: Be sure to write "0" to this bit.
Page 612: Operation Of The Low-Voltage/Cpu Operation Detection Reset Circuit
CHAPTER 20 LOW-VOLTAGE/CPU OPERATION DETECTION RESET CIRCUIT 20.4 Operation of the Low-voltage/CPU Operation Detection MB90930 Series Reset Circuit 20.4 Operation of the Low-voltage/CPU Operation Detection Reset Circuit This circuit is used to monitor the power supply voltage. If the power supply voltage is lower than the setting value, this circuit generates an internal reset.
Page 613: Notes On Using The Low-Voltage/Cpu Operation Detection Reset Circuit
CHAPTER 20 LOW-VOLTAGE/CPU OPERATION DETECTION RESET CIRCUIT 20.5 Notes on Using the Low-voltage/CPU Operation Detection MB90930 Series Reset Circuit 20.5 Notes on Using the Low-voltage/CPU Operation Detection Reset Circuit This section provides notes on using the low-voltage/CPU operation detection reset circuit.
Page 614: Sample Program For The Low-Voltage/Cpu Operation Detection Reset Circuit
CHAPTER 20 LOW-VOLTAGE/CPU OPERATION DETECTION RESET CIRCUIT 20.6 Sample Program for the Low-voltage/CPU Operation MB90930 Series Detection Reset Circuit 20.6 Sample Program for the Low-voltage/CPU Operation Detection Reset Circuit This section provides a sample program for the low-voltage/CPU operation detection reset circuit.
Page 615: Chapter 21 Stepping Motor Controller
This chapter explains the function and operation of a stepping motor controller. 21.1 Overview of Stepping Motor Controller 21.2 Registers for Stepping Motor Controller 21.3 Operation of Stepping Motor Controller 21.4 Cautions when Using Stepping Motor Controller CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 616: Overview Of Stepping Motor Controller
CHAPTER 21 STEPPING MOTOR CONTROLLER 21.1 Overview of Stepping Motor Controller MB90930 Series 21.1 Overview of Stepping Motor Controller The stepping motor controller consists of these; Two PWM pulse generators, four motor drivers and selector logic. The four motor drivers have a high-output driving capability, and two motor coils can be connected directly to four pins.
Page 617: Registers For Stepping Motor Controller
CHAPTER 21 STEPPING MOTOR CONTROLLER 21.2 Registers for Stepping Motor Controller MB90930 Series 21.2 Registers for Stepping Motor Controller There are five types of registers for the stepping motor controller: • PWM Control register • PWM1 Compare register • PWM2 Compare register •...
Page 618: Pwm Control Register
CHAPTER 21 STEPPING MOTOR CONTROLLER 21.2 Registers for Stepping Motor Controller MB90930 Series 21.2.1 PWM Control Register The PWM control register starts/stops the stepping motor controller, and performs interrupt control, and performs setting of external output pins, etc., for the stepping motor controller.
Page 619 CHAPTER 21 STEPPING MOTOR CONTROLLER 21.2 Registers for Stepping Motor Controller MB90930 Series [bit5, bit4] P1, P0: Operating clock select bits (bits to select operating clock) The P1 and P0 bits specify the clock input signal for the PWM pulse generator.
Page 620: Pwm1&2 Compare Registers
CHAPTER 21 STEPPING MOTOR CONTROLLER 21.2 Registers for Stepping Motor Controller MB90930 Series 21.2.2 PWM1&2 Compare Registers The value of the two 8(10) bits compare register of PWM1&2 determine the width of the PWM pulse. The stored "00 (000 )" value indicates that the PWM duty is 0%, and the stored "FF...
Page 621 CHAPTER 21 STEPPING MOTOR CONTROLLER 21.2 Registers for Stepping Motor Controller MB90930 Series Figure 21.2-1 Relationship between the Compare Register Setting Value and PWM Pulse Width Register value One PWM cycle 256 (1024) input cycles (200 128 (512) input cycle...
Page 622: Pwm1&2 Selection Registers
CHAPTER 21 STEPPING MOTOR CONTROLLER 21.2 Registers for Stepping Motor Controller MB90930 Series 21.2.3 PWM1&2 Selection Registers The PWM1&2 selection registers determine whether to set the output of the external pin of the stepping motor controller to "0", "1", PWM pulse, or high impedance.
Page 623 CHAPTER 21 STEPPING MOTOR CONTROLLER 21.2 Registers for Stepping Motor Controller MB90930 Series Figure 21.2-2 load timing of PWM compare register value [Automatic clear of BS bit] Load the values of the registers and PWM 1 cycle reflected in the output signal.
Page 624 CHAPTER 21 STEPPING MOTOR CONTROLLER 21.2 Registers for Stepping Motor Controller MB90930 Series [bit13 to bit11] P2 to P0: Output select bits These bits are used to select the output signal for PWM2Px. [bit10 to bit8] M2 to M0: Output select bits These bits are used to select the output signal for PWM2Mx.
Page 625: Operation Of Stepping Motor Controller
CHAPTER 21 STEPPING MOTOR CONTROLLER 21.3 Operation of Stepping Motor Controller MB90930 Series 21.3 Operation of Stepping Motor Controller The operation of the stepping motor controller is explained. ■ Setting Operation of Stepping Motor Controller Figure 21.3-1 Setting of Stepping Motor Controller PWM1 H width (compare value) is set.
Page 626 CHAPTER 21 STEPPING MOTOR CONTROLLER 21.3 Operation of Stepping Motor Controller MB90930 Series Figure 21.3-2 Examples of PWM1&2 Waveform Output When the value of compare register is "00 "/"000 "(duty ratio is 0%): Value of counter: PWM waveform: When the value of compare register is "80 "/"200...
Page 627: Cautions When Using Stepping Motor Controller
CHAPTER 21 STEPPING MOTOR CONTROLLER 21.4 Cautions when Using Stepping Motor Controller MB90930 Series 21.4 Cautions when Using Stepping Motor Controller The cautions when using the stepping motor controller are described below. ■ Cautions when Changing PWM Setting The PWM compare registers 1&2 (PWC1n, PWC2n) and the PWM selection registers 1&2 (PWS1n, PWS2n) can be accessed at any time.
Page 628 CHAPTER 21 STEPPING MOTOR CONTROLLER 21.4 Cautions when Using Stepping Motor Controller MB90930 Series FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 629: Chapter 22 Sound Generator
CHAPTER 22 SOUND GENERATOR This chapter describes the functions and operations of the sound generator. 22.1 Outline of the Sound Generator 22.2 Registers of the Sound Generator CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 630: Outline Of The Sound Generator
CHAPTER 22 SOUND GENERATOR 22.1 Outline of the Sound Generator MB90930 Series 22.1 Outline of the Sound Generator The sound generator contains the sound control register, frequency data register, amplitude data register, decrement grade register, tone count register, PWM pulse generator, frequency counter, decrement counter, and tone pulse counter.
Page 631: Registers Of The Sound Generator
CHAPTER 22 SOUND GENERATOR 22.2 Registers of the Sound Generator MB90930 Series 22.2 Registers of the Sound Generator The sound generator has the following 5 types of registers. • Sound control registers (SGCRH0/SGCRH1, SGCRL0/SGCRL1) • Frequency data registers (SGFR0/SGFR1) • Amplitude data registers (SGAR0/SGAR1) •...
Page 632 CHAPTER 22 SOUND GENERATOR 22.2 Registers of the Sound Generator MB90930 Series Figure 22.2-1 Registers of the Sound Generator Upper bits in the sound control register (GCRH0, SGCRH1) Address: 00005B BUSY Address: 0000D9 served (R/W) (R/W) (R/W) Initial value →...
Page 633: Sound Control Register(Sgcrh0/Sgcrh1, Sgcrl0/Sgcrl1)
CHAPTER 22 SOUND GENERATOR 22.2 Registers of the Sound Generator MB90930 Series 22.2.1 Sound Control Register (SGCRH0/SGCRH1, SGCRL0/SGCRL1) The sound control register controls the operating status by controlling the interrupt of the sound generator and setting its external output pins.
Page 634 CHAPTER 22 SOUND GENERATOR 22.2 Registers of the Sound Generator MB90930 Series [bit7, bit6] S1, S0: Operation clock select bits This bit group specifies the clock input signal for the sound generator. Clock input Machine Clock 1/2 machine clock 1/4 machine clock...
Page 635: Frequency Data Register(Sgfr0/Sgfr1)
CHAPTER 22 SOUND GENERATOR 22.2 Registers of the Sound Generator MB90930 Series 22.2.2 Frequency Data Register(SGFR0/SGFR1) The frequency data register stores the reload value for the frequency counter. The value stored indicates the frequency of sound (or tone signal from the toggle flip-flop).
Page 636: Amplitude Data Register(Sgar0/Sgar1)
CHAPTER 22 SOUND GENERATOR 22.2 Registers of the Sound Generator MB90930 Series 22.2.3 Amplitude Data Register(SGAR0/SGAR1) The amplitude data register stores the reload value for the PWM pulse generator. The register value indicates the sound amplitude. It is reloaded to the PWM pulse generator each time a tone cycle ends.
Page 637: Decrement Grade Register(Sgdr0/Sgdr1)
CHAPTER 22 SOUND GENERATOR 22.2 Registers of the Sound Generator MB90930 Series 22.2.4 Decrement Grade Register(SGDR0/SGDR1) The decrement grade register stores the reload value for the decrement counter. The register is to automatically decrement the value held in the amplitude data register.
Page 638: Tone Count Register(Sgtr0/Sgtr1)
CHAPTER 22 SOUND GENERATOR 22.2 Registers of the Sound Generator MB90930 Series 22.2.5 Tone Count Register(SGTR0/SGTR1) The tone count register stores the reload value for the tone pulse counter. The tone pulse counter counts the number of tone pulses (or the number of decrement operations), and sets the INT bit when it reaches to the reload value.
Page 639: Chapter 23 Rom Mirror Function Select Module
CHAPTER 23 ROM MIRROR FUNCTION SELECT MODULE This chapter describes the ROM mirror function select module. 23.1 Outline of the ROM Mirror Function Select Module 23.2 ROM Mirror Function Select Register (ROMM) CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 640: Outline Of The Rom Mirror Function Select Module
CHAPTER 23 ROM MIRROR FUNCTION SELECT MODULE 23.1 Outline of the ROM Mirror Function Select Module MB90930 Series 23.1 Outline of the ROM Mirror Function Select Module The ROM mirror function select module can be used to select the viewing of bank FF via bank 00 by setting its register.
Page 641: Rom Mirror Function Select Register (Romm)
CHAPTER 23 ROM MIRROR FUNCTION SELECT MODULE 23.2 ROM Mirror Function Select Register (ROMM) MB90930 Series 23.2 ROM Mirror Function Select Register (ROMM) Do not access the ROM mirror function select register (ROMM) with address 008000 to 00FFFF being used.
Page 642 CHAPTER 23 ROM MIRROR FUNCTION SELECT MODULE 23.2 ROM Mirror Function Select Register (ROMM) MB90930 Series ■ Memory Space Figure 23.2-2 shows memory space. Figure 23.2-2 Memory Space FFFFFF ROM area ROM area 010000 ROM mirror area 008000 RAM area...
Page 643: Chapter 24 1M-Bit Flash Memory
24.3 Flash Memory Control Status Register (FMCS) 24.4 Flash Memory Write Control Registers (FWR0/FWR1) 24.5 Starting the Flash Memory Automatic Algorithm 24.6 Confirming the Automatic Algorithm Execution State 24.7 Writing/Erasing Flash Memory 24.8 Flash Security Function CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 644: Overview Of 1M-Bit Flash Memory
CHAPTER 24 1M-BIT FLASH MEMORY 24.1 Overview of 1M-bit Flash Memory MB90930 Series 24.1 Overview of 1M-bit Flash Memory The 1M-bit flash memory is mapped into the FE to FF banks on the CPU memory map. The flash memory interface circuit allows the CPU to read- access and program-access the flash memory in the same way as for masked ROM.
Page 645: Sector Configuration Of 1M-Bit Flash Memory
CHAPTER 24 1M-BIT FLASH MEMORY 24.2 Sector Configuration of 1M-bit Flash Memory MB90930 Series 24.2 Sector Configuration of 1M-bit Flash Memory This section shows the sector configuration of the 1M-bit flash memory. ■ Sector Configuration Figure 24.2-1 illustrates the sector configuration of the 1M-bit flash memory. The addresses in the figure indicate the upper and lower addresses of each sector.
Page 646: Flash Memory Control Status Register (Fmcs)
CHAPTER 24 1M-BIT FLASH MEMORY 24.3 Flash Memory Control Status Register (FMCS) MB90930 Series 24.3 Flash Memory Control Status Register (FMCS) The flash memory control status resister (FMCS), located in the flash memory interface circuit, is used for the writing/erasing operation on the flash memory.
Page 647 CHAPTER 24 1M-BIT FLASH MEMORY 24.3 Flash Memory Control Status Register (FMCS) MB90930 Series [bit5] WE: Write Enable This bit is a write enable bit to flash memory area. When this bit is "1", the write after a command sequence (see Section "24.5 Starting the Flash Memory Automatic Algorithm") issued to the FC to FF bank is to flash memory.
Page 648: Flash Memory Write Control Registers (Fwr0/Fwr1)
CHAPTER 24 1M-BIT FLASH MEMORY 24.4 Flash Memory Write Control Registers (FWR0/FWR1) MB90930 Series 24.4 Flash Memory Write Control Registers (FWR0/ FWR1) The flash memory write control registers (FWR0/FWR1) exist in the flash memory interface to be used to set the flash memory write-protect feature.
Page 649 CHAPTER 24 1M-BIT FLASH MEMORY 24.4 Flash Memory Write Control Registers (FWR0/FWR1) MB90930 Series Table 24.4-1 Functions of Flash Memory Write Control Registers (FWR0/FWR1) Bit name Function bit15 Reserved bits For programming, be sure to write "0" to these bits. The values read from the bits are indefinite.
Page 650 CHAPTER 24 1M-BIT FLASH MEMORY 24.4 Flash Memory Write Control Registers (FWR0/FWR1) MB90930 Series Figure 24.4-2 Flash Memory Write-disable/enable/protect States in Flash Memory Write Control Register (FWR0/FWR1) Register Register Initialize Initialize write write Write- Write-enable Write-protect Write-disable disable SA0E Write-...
Page 651 CHAPTER 24 1M-BIT FLASH MEMORY 24.4 Flash Memory Write Control Registers (FWR0/FWR1) MB90930 Series ■ Setup Flowchart for Flash Memory Write Control Registers (FWR0/FWR1) Set the FMCS:WE bit and write-permit or write-protect each sector by setting the corresponding bit in the flash memory write control register (FWR0/FWR1) to "1" or "0", respectively.
Page 652 CHAPTER 24 1M-BIT FLASH MEMORY 24.4 Flash Memory Write Control Registers (FWR0/FWR1) MB90930 Series ■ Note on Setting the FMCS:WE Bit To program into flash memory, set FMCS:WE to "1" to write-permit it and set the flash memory write control register (FWR0/FWR1). When FMCS:WE inhibits writing (contains "0"), the write to flash memory is not operated even though it is permitted by the flash memory...
Page 653: Starting The Flash Memory Automatic Algorithm
CHAPTER 24 1M-BIT FLASH MEMORY 24.5 Starting the Flash Memory Automatic Algorithm MB90930 Series 24.5 Starting the Flash Memory Automatic Algorithm Four types of commands are available for starting the flash memory automatic algorithm: Read/Reset, Write, Chip Erase, and Sector Erase. Control of suspend and restart is enabled for Sector erase.
Page 654: Confirming The Automatic Algorithm Execution State
CHAPTER 24 1M-BIT FLASH MEMORY 24.6 Confirming the Automatic Algorithm Execution State MB90930 Series 24.6 Confirming the Automatic Algorithm Execution State Because the write/erase flow of the flash memory is controlled using the automatic algorithm, the flash memory has hardware sequence flags for informing its internal operating state and completion of operation.
Page 655: Data Polling Flag (Dq7)
CHAPTER 24 1M-BIT FLASH MEMORY 24.6 Confirming the Automatic Algorithm Execution State MB90930 Series 24.6.1 Data Polling Flag (DQ7) The data polling flag (DQ7) is to indicate that the automatic algorithm is being executed or has terminated by the data polling function.
Page 656: Toggle Bit Flag (Dq6)
CHAPTER 24 1M-BIT FLASH MEMORY 24.6 Confirming the Automatic Algorithm Execution State MB90930 Series 24.6.2 Toggle Bit Flag (DQ6) In the same manner of the data polling flag (DQ7), the toggle bit flag (DQ6) is to indicate that the automatic algorithm is being executed or has terminated by the toggle bit function.
Page 657: Timing Limit Exceeded Flag (Dq5)
CHAPTER 24 1M-BIT FLASH MEMORY 24.6 Confirming the Automatic Algorithm Execution State MB90930 Series 24.6.3 Timing Limit Exceeded Flag (DQ5) The timing limit excess flag (DQ5) indicates that the automatic algorithm has exceeded the time (internal pulse count) specified inside the flash memory.
Page 658: Sector Erase Timer Flag (Dq3)
CHAPTER 24 1M-BIT FLASH MEMORY 24.6 Confirming the Automatic Algorithm Execution State MB90930 Series 24.6.4 Sector Erase Timer Flag (DQ3) The sector erase timer flag (DQ3) is to indicate whether the automatic algorithm is being executed during the sector erase wait period after the Sector Erase command has been started.
Page 659: Writing/Erasing Flash Memory
CHAPTER 24 1M-BIT FLASH MEMORY 24.7 Writing/Erasing Flash Memory MB90930 Series 24.7 Writing/Erasing Flash Memory This section describes each operation of flash memory Write/Erase with activation of the automatic algorithm. ■ Writing/Erasing Flash Memory The automatic algorithm can be activated by writing either command sequence of the Read/ Reset, Write, Chip Erase, Sector Erase, Sector Erase Suspend, or Erase Restart (see Table 24.5-...
Page 660: Setting Flash Memory To The Read/Reset State
CHAPTER 24 1M-BIT FLASH MEMORY 24.7 Writing/Erasing Flash Memory MB90930 Series 24.7.1 Setting Flash Memory to the Read/Reset State This section describes the procedure for issuing the Read/Reset command to set the flash memory to the read/reset state. ■ Setting Flash Memory to the Read/Reset State To set the flash memory to the read/reset state, issue the Read/Reset command in the command sequence table (see Table 24.5-1) continuously to the target sector in flash memory.
Page 661: Writing Data To Flash Memory
CHAPTER 24 1M-BIT FLASH MEMORY 24.7 Writing/Erasing Flash Memory MB90930 Series 24.7.2 Writing Data to Flash Memory This section describes the procedure for issuing the Write command to write data to the flash memory. ■ Writing Data to the Flash Memory To start the automatic algorithm for writing data into flash memory, issue the write command in the command sequence table (see Table 24.5-1) continuously to the target sector in flash...
Page 662 CHAPTER 24 1M-BIT FLASH MEMORY 24.7 Writing/Erasing Flash Memory MB90930 Series ■ Writing Procedure to the Flash Memory Figure 24.7-1 shows an example of the procedure for writing to the flash memory. The hardware sequence flags (see Section "24.6 Confirming the Automatic Algorithm Execution State") can be used to determine the state of the automatic algorithm in the flash memory.
Page 663: Erasing All Data Of Flash Memory (Chip Erase)
CHAPTER 24 1M-BIT FLASH MEMORY 24.7 Writing/Erasing Flash Memory MB90930 Series 24.7.3 Erasing All Data of Flash Memory (Chip Erase) This section describes the procedure for issuing the Chip Erase command to erase all data in the flash memory. ■ Erasing All Data of Flash Memory (Chip Erase) To erase all data from flash memory, issue the Chip Erase command in the command sequence table (see Table 24.5-1) continuously to the target sectors in flash memory.
Page 664: Erasing Arbitrary Data Of Flash Memory (Sector Erase)
CHAPTER 24 1M-BIT FLASH MEMORY 24.7 Writing/Erasing Flash Memory MB90930 Series 24.7.4 Erasing Arbitrary Data of Flash Memory (Sector Erase) This section describes the procedure for issuing the Sector Erase command to erase one or more optional sectors in flash memory. The data by individual sector can be erased.
Page 665 CHAPTER 24 1M-BIT FLASH MEMORY 24.7 Writing/Erasing Flash Memory MB90930 Series Figure 24.7-2 Example of Procedure for Erasing Sectors in the Flash Memory Erase start FMCS:WE (bit5) Flash memory erase enabled Erase command sequence (1) yyyAAA XXAA (2) yyy554 XX55...
Page 666: Suspending Sector Erase Of Flash Memory
CHAPTER 24 1M-BIT FLASH MEMORY 24.7 Writing/Erasing Flash Memory MB90930 Series 24.7.5 Suspending Sector Erase of Flash Memory This section describes the procedure for issuing the Sector Erase Suspend command to suspend erasing of flash memory sectors. During the suspension, data can be read from sectors that are not being erased.
Page 667: Restarting Sector Erase Of Flash Memory
CHAPTER 24 1M-BIT FLASH MEMORY 24.7 Writing/Erasing Flash Memory MB90930 Series 24.7.6 Restarting Sector Erase of Flash Memory This section describes the procedure for issuing the Sector Erase Restart command to restart suspended erasing of flash memory sectors. ■ Restarting Sector Erase of Flash Memory To restart a suspended sector erase operation, issue the Sector Erase Restart command in the command sequence table (see Table 24.5-1) to flash memory.
Page 668: Flash Security Function
CHAPTER 24 1M-BIT FLASH MEMORY 24.8 Flash Security Function MB90930 Series 24.8 Flash Security Function The flash security function enables to protect the contents in the flash memory. ■ Overview of Flash Security Function If protection code "01 " is written in the security bit, the flash memory is in the protected state by security.
Page 669: Chapter 25 Examples Of Serial Programming Connection
Yokogawa Digital Computer Corporation. 25.1 Basic Configuration for Serial Programming Connection 25.2 Example of Connection in Single-Chip Mode (Using Power from User System) 25.3 Example of Connection with Flash Microcontroller Programmer (Using Power from the User System) CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 670: Basic Configuration For Serial Programming Connection
25.1 Basic Configuration for Serial Programming Connection The flash memory product supports serial onboard programming (Fujitsu standard) of flash ROM. This section provides the relevant specifications. ■ Basic Configuration of Serial Programming Connection Fujitsu-standard serial onboard programming uses the AF220/AF210/AF120/AF110 flash microcontroller programmer manufactured by Yokogawa Digital Computer Corporation.
Page 671 25.1 Basic Configuration for Serial Programming Connection MB90930 Series ■ Pins Used for Fujitsu Standard Serial On-board Writing Table 25.1-1 shows the functions of the related pins used for Fujitsu Standard serial on-board writing. Table 25.1-1 Pins Used for Fujitsu-standard Serial Onboard Programming...
Page 672 CHAPTER 25 EXAMPLES OF SERIAL PROGRAMMING CONNECTION 25.1 Basic Configuration for Serial Programming Connection MB90930 Series ■ Oscillator Clock Frequency and Serial Clock Input Frequency The serial clock frequency of the flash memory product that can be input can be derived by the formula shown below.
Page 673 CHAPTER 25 EXAMPLES OF SERIAL PROGRAMMING CONNECTION 25.1 Basic Configuration for Serial Programming Connection MB90930 Series ■ System Configuration of Flash Microcontroller Programmer Table 25.1-3 shows the system configuration of the flash microcontroller programmer. Table 25.1-3 System Configuration of the Flash Microcontroller Programmer...
Page 674: Example Of Connection In Single-Chip Mode (Using Power From User System)
CHAPTER 25 EXAMPLES OF SERIAL PROGRAMMING CONNECTION 25.2 Example of Connection in Single-Chip Mode (Using Power MB90930 Series from User System) 25.2 Example of Connection in Single-Chip Mode (Using Power from User System) In the user system, mode pins MD2 and MD0, which are set to single-chip...
Page 675 CHAPTER 25 EXAMPLES OF SERIAL PROGRAMMING CONNECTION 25.2 Example of Connection in Single-Chip Mode (Using Power MB90930 Series from User System) Using the P00, SIN1, SOT1, and SCK1 pins in the user system requires a control circuit as shown in Figure 25.2-2 (the user circuit is disconnected in serial programming mode by outputting "L"...
Page 676: Example Of Connection With Flash Microcontroller Programmer (Using Power From The User System)
CHAPTER 25 EXAMPLES OF SERIAL PROGRAMMING CONNECTION 25.3 Example of Connection with Flash Microcontroller MB90930 Series Programmer (Using Power from the User System) 25.3 Example of Connection with Flash Microcontroller Programmer (Using Power from the User System) If, in serial programming mode, pins (MD2, MD0 and P00) are set as shown below, MD2, MD0, and P00 do not need to be connected with the flash microcontroller programmer.
Page 677 CHAPTER 25 EXAMPLES OF SERIAL PROGRAMMING CONNECTION 25.3 Example of Connection with Flash Microcontroller MB90930 Series Programmer (Using Power from the User System) Using the P00, SIN1, SOT1, and SCK1 pins in the user system requires a control circuit as shown in Figure 25.3-2 (the user circuit is disconnected in serial programming mode by...
Page 678 CHAPTER 25 EXAMPLES OF SERIAL PROGRAMMING CONNECTION 25.3 Example of Connection with Flash Microcontroller MB90930 Series Programmer (Using Power from the User System) FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 679: Chapter 26 Rom Security Function
CHAPTER 26 ROM SECURITY FUNCTION This chapter explains the ROM security function. 26.1 Overview of ROM Security Function CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 680: Overview Of Rom Security Function
The ROM security function protects the content of ROM. ■ Overview of ROM Security Function The ROM security function is to avoid disclosing the ROM data to third parties by restricting the access to ROM. Please contact Fujitsu Microelectronics for details of this function. FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 681: Chapter 27 Address Match Detection Function
CHAPTER 27 ADDRESS MATCH DETECTION FUNCTION This chapter describes the functions and operations of the address match detection function. 27.1 Outline of the Address Match Detection Function 27.2 Sample Application of the Address Match Detection Function CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 682: Outline Of The Address Match Detection Function
CHAPTER 27 ADDRESS MATCH DETECTION FUNCTION 27.1 Outline of the Address Match Detection Function MB90930 Series 27.1 Outline of the Address Match Detection Function Once the address matches the setting value in the address detection register, the INT9 instruction is executed. Once the INT9 interrupt service routine is processed, the address match can be detected.
Page 683 CHAPTER 27 ADDRESS MATCH DETECTION FUNCTION 27.1 Outline of the Address Match Detection Function MB90930 Series ■ Program Address Detection Registers (PADR0/PADR1) The program address detection register holds the address to be compared with the program counter value. When the address of the instruction executed by the program matches the set value, with the PACSR interrupt enable bit "1", this module requests the CPU to execute the...
Page 684 CHAPTER 27 ADDRESS MATCH DETECTION FUNCTION 27.1 Outline of the Address Match Detection Function MB90930 Series [bit1] AD0E (Compare Enable 0) This bit enables the operation of PADR0. If the PADR0 register value matches the address with this bit "1", the INT9 instruction is issued to the CPU.
Page 685: Sample Application Of The Address Match Detection Function
CHAPTER 27 ADDRESS MATCH DETECTION FUNCTION 27.2 Sample Application of the Address Match Detection MB90930 Series Function 27.2 Sample Application of the Address Match Detection Function The address match detection can be functioned by providing the E PROM and storing correction-related information and patch programs in it. The CPU...
Page 686 CHAPTER 27 ADDRESS MATCH DETECTION FUNCTION 27.2 Sample Application of the Address Match Detection MB90930 Series Function Note: PROM in the initial state must be all "0". FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 687: Example Of Program Error Correction
CHAPTER 27 ADDRESS MATCH DETECTION FUNCTION 27.2 Sample Application of the Address Match Detection MB90930 Series Function 27.2.1 Example of Program Error Correction The main part of the patch program and its program address are transferred to the MCU via the connector (UART). The MCU writes the information to E PROM.
Page 688: Example Of Correction Processing
CHAPTER 27 ADDRESS MATCH DETECTION FUNCTION 27.2 Sample Application of the Address Match Detection MB90930 Series Function 27.2.2 Example of Correction Processing The MCU reads the E PROM value after a reset. If the byte count of the patch program is not "0", the MCU reads the main part of the patch program and writes it to RAM.
Page 689 CHAPTER 27 ADDRESS MATCH DETECTION FUNCTION 27.2 Sample Application of the Address Match Detection MB90930 Series Function Figure 27.2-4 Diagram of Address Match Detection Function Processing MB90930 series FFFFFF FF0050 Abnormal program FF0000 PROM FFFF FE0000 0090 Corrected program 001100...
Page 690 CHAPTER 27 ADDRESS MATCH DETECTION FUNCTION 27.2 Sample Application of the Address Match Detection MB90930 Series Function FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 691: Appendix
APPENDIX The appendix provides the I/O map and describes the available instructions. APPENDIX A I/O Maps APPENDIX B Instructions CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 692: Appendix A I/O Maps
APPENDIX APPENDIX A I/O Maps MB90930 Series APPENDIX A I/O Maps The registers of individual peripheral resources are assigned the following addresses. Table A-1 and Table A-2 list the addresses assigned for the registers of individual peripheral resources. Table A-1 I/O Map (1 / 12)
Page 693 APPENDIX APPENDIX A I/O Maps MB90930 Series Table A-1 I/O Map (2 / 12) Peripheral Address Register Name Abbreviation Access Initial Value Functions XX000000 Port 1 direction register DDR1 Port 1 000000XX Port 2 direction register DDR2 Port 2 00000000...
Page 694 APPENDIX APPENDIX A I/O Maps MB90930 Series Table A-1 I/O Map (3 / 12) Peripheral Address Register Name Abbreviation Access Initial Value Functions XXXXXXXX Compare clear register CPCLR XXXXXXXX 00000000 Timer data register TCDT 16bit free-run timer 00000000 Timer control status...
Page 695 APPENDIX APPENDIX A I/O Maps MB90930 Series Table A-1 I/O Map (4 / 12) Peripheral Address Register Name Abbreviation Access Initial Value Functions 00000000 Serial mode register 0 SMR0 R/W, W 00000000 Serial control register 0 SCR0 R/W, W Reception/Transmission...
Page 696 APPENDIX APPENDIX A I/O Maps MB90930 Series Table A-1 I/O Map (5 / 12) Peripheral Address Register Name Abbreviation Access Initial Value Functions LCD output control 00000000 LOCR1 register 1 LCDC LCD output control 00000000 LOCR2 register 2 Sound control register 0...
Page 697 APPENDIX APPENDIX A I/O Maps MB90930 Series Table A-1 I/O Map (6 / 12) Peripheral Address Register Name Abbreviation Access Initial Value Functions Low voltage/CPU Low voltage/CPU operation 00111000 LVRC operation detection detection reset control reset register XXXXXXX1 ROM mirror register...
Page 698 APPENDIX APPENDIX A I/O Maps MB90930 Series Table A-1 I/O Map (7 / 12) Peripheral Address Register Name Abbreviation Access Initial Value Functions (Not available) LCD output control XXXXX111 LOCR3 LCDC register 1 (Not available) 00000000 A/D setting register 0...
Page 699 APPENDIX APPENDIX A I/O Maps MB90930 Series Table A-1 I/O Map (8 / 12) Peripheral Address Register Name Abbreviation Access Initial Value Functions Interrupt control register 00000111 ICR00 Interrupt control register 00000111 ICR01 Interrupt control register 00000111 ICR02 Interrupt control register...
Page 700 APPENDIX APPENDIX A I/O Maps MB90930 Series Table A-1 I/O Map (9 / 12) Peripheral Address Register Name Abbreviation Access Initial Value Functions 00000000 Serial mode register 1 SMR1 R/W, W 00000000 Serial control register 1 SCR1 R/W, W Reception/Transmission...
Page 701 APPENDIX APPENDIX A I/O Maps MB90930 Series Table A-1 I/O Map (10 / 12) Peripheral Address Register Name Abbreviation Access Initial Value Functions Input capture control 00000000 ICS67 status register 6/7 Input capture 6/7 Input capture edge register XXX0X0XX ICE67...
Page 702 APPENDIX APPENDIX A I/O Maps MB90930 Series Table A-1 I/O Map (11 / 12) Peripheral Address Register Name Abbreviation Access Initial Value Functions 00000000 Serial mode register 2 SMR2 R/W, W 00000000 Serial control register 2 SCR2 R/W, W Reception/Transmission...
Page 703 APPENDIX APPENDIX A I/O Maps MB90930 Series Table A-1 I/O Map (12 / 12) Peripheral Address Register Name Abbreviation Access Initial Value Functions Extended status Control 00000100 ESCR3 Register 3 Baud Rate Generator UART 00000000 BGR30 Register 30 (LIN/SCI) 3...
Page 704 APPENDIX APPENDIX A I/O Maps MB90930 Series Table A-2 I/O Map (1 / 18) Peripheral Address Register Name Abbreviation Access Initial Value Functions 3700 (Not available) 390F 3910 (Not available) 391F 3920 11111111 PPG0 down counter register PDCR0 3921 11111111...
Page 705 APPENDIX APPENDIX A I/O Maps MB90930 Series Table A-2 I/O Map (2 / 18) Peripheral Address Register Name Abbreviation Access Initial Value Functions 3937 (Not available) 393F 3940 XXXXXXXX Input capture register 4 IPCP4 3941 XXXXXXXX Input capture 4/5 3942...
Page 706 APPENDIX APPENDIX A I/O Maps MB90930 Series Table A-2 I/O Map (3 / 18) Peripheral Address Register Name Abbreviation Access Initial Value Functions 3960 XXXXXXXX 3961 XXXXXXXX 3962 XXXXXXXX 3963 XXXXXXXX 3964 XXXXXXXX 3965 XXXXXXXX 3966 XXXXXXXX 3967 XXXXXXXX 3968...
Page 707 APPENDIX APPENDIX A I/O Maps MB90930 Series Table A-2 I/O Map (4 / 18) Peripheral Address Register Name Abbreviation Access Initial Value Functions 3980 XXXXXXXX PWM1 compare register 0 PWC10 3981 XXXXXXXX 3982 XXXXXXXX Stepping motor PMW2 compare register 0...
Page 708 APPENDIX APPENDIX A I/O Maps MB90930 Series Table A-2 I/O Map (5 / 18) Peripheral Address Register Name Abbreviation Access Initial Value Functions 399E (Not available) 39A5 39A6 Flash writing control register 0 00000000 FWR0 Flash I/F 39A7 Flash writing...
Page 709 APPENDIX APPENDIX A I/O Maps MB90930 Series Table A-2 I/O Map (6 / 18) Peripheral Address Register Name Abbreviation Access Initial Value Functions 39F0 11111111 PPG5 down counter register PDCR5 39F1 11111111 39F2 11111111 PPG5 cycle setting register PCSR5 39F3...
Page 710 APPENDIX APPENDIX A I/O Maps MB90930 Series Table A-2 I/O Map (7 / 18) Peripheral Address Register Name Abbreviation Access Initial Value Functions 3B00 XXXXXXXX 3B01 XXXXXXXX 3B02 XXXXXXXX 3B03 XXXXXXXX 3B04 XXXXXXXX 3B05 XXXXXXXX 3B06 XXXXXXXX 3B07 XXXXXXXX 3B08...
Page 711 APPENDIX APPENDIX A I/O Maps MB90930 Series Table A-2 I/O Map (8 / 18) Peripheral Address Register Name Abbreviation Access Initial Value Functions 3B1C XXXXXXXX 3B1D XXXXXXXX General-purpose RAM CAN-RAM (R/W) 3B1E XXXXXXXX 3B1F XXXXXXXX 3B20 XXXXXXXX 3B21 XXXXXXXX ID register 0...
Page 712 APPENDIX APPENDIX A I/O Maps MB90930 Series Table A-2 I/O Map (9 / 18) Peripheral Address Register Name Abbreviation Access Initial Value Functions 3B38 XXXXXXXX 3B39 XXXXXXXX ID register 6 IDR6 (R/W) 3B3A XXXXXXXX 3B3B XXXXXXXX 3B3C XXXXXXXX 3B3D XXXXXXXX...
Page 713 APPENDIX APPENDIX A I/O Maps MB90930 Series Table A-2 I/O Map (10 / 18) Peripheral Address Register Name Abbreviation Access Initial Value Functions 3B54 XXXXXXXX 3B55 XXXXXXXX ID register 13 IDR13 (R/W) 3B56 XXXXXXXX 3B57 XXXXXXXX 3B58 XXXXXXXX 3B59 XXXXXXXX...
Page 714 APPENDIX APPENDIX A I/O Maps MB90930 Series Table A-2 I/O Map (11 / 18) Peripheral Address Register Name Abbreviation Access Initial Value Functions 3B70 XXXXXXXX DLC register 8 DLCR8 (R/W) 3B71 XXXXXXXX 3B72 XXXXXXXX DLC register 9 DLCR9 (R/W) 3B73...
Page 715 APPENDIX APPENDIX A I/O Maps MB90930 Series Table A-2 I/O Map (12 / 18) Peripheral Address Register Name Abbreviation Access Initial Value Functions 3B88 XXXXXXXX 3B89 XXXXXXXX 3B8A XXXXXXXX 3B8B XXXXXXXX Data register 1 (8 bytes) DTR1 (R/W) 3B8C XXXXXXXX...
Page 716 APPENDIX APPENDIX A I/O Maps MB90930 Series Table A-2 I/O Map (13 / 18) Peripheral Address Register Name Abbreviation Access Initial Value Functions 3BA0 XXXXXXXX 3BA1 XXXXXXXX 3BA2 XXXXXXXX 3BA3 XXXXXXXX Data register 4 (8 bytes) DTR4 (R/W) 3BA4 XXXXXXXX...
Page 717 APPENDIX APPENDIX A I/O Maps MB90930 Series Table A-2 I/O Map (14 / 18) Peripheral Address Register Name Abbreviation Access Initial Value Functions 3BB8 XXXXXXXX 3BB9 XXXXXXXX 3BBA XXXXXXXX 3BBB XXXXXXXX Data register 7 (8 bytes) DTR7 (R/W) 3BBC XXXXXXXX...
Page 718 APPENDIX APPENDIX A I/O Maps MB90930 Series Table A-2 I/O Map (15 / 18) Peripheral Address Register Name Abbreviation Access Initial Value Functions 3BD0 XXXXXXXX 3BD1 XXXXXXXX 3BD2 XXXXXXXX 3BD3 XXXXXXXX Data register 10 (8 bytes) DTR10 (R/W) 3BD4 XXXXXXXX...
Page 719 APPENDIX APPENDIX A I/O Maps MB90930 Series Table A-2 I/O Map (16 / 18) Peripheral Address Register Name Abbreviation Access Initial Value Functions 3BE8 XXXXXXXX 3BE9 XXXXXXXX 3BEA XXXXXXXX 3BEB XXXXXXXX Data register 13 (8 bytes) DTR13 (R/W) 3BEC XXXXXXXX...
Page 720 APPENDIX APPENDIX A I/O Maps MB90930 Series Table A-2 I/O Map (17 / 18) Peripheral Address Register Name Abbreviation Access Initial Value Functions 3D02 000X0000 Last event indicator register LEIR (R/W) 3D03 XXXXXXXX 3D04 00000000 RX/TX error counter RTEC 3D05...
Page 721 APPENDIX APPENDIX A I/O Maps MB90930 Series Table A-2 I/O Map (18 / 18) Peripheral Address Register Name Abbreviation Access Initial Value Functions 3D14 XXXXXXXX 3D15 XXXXXXXX Acceptance mask register 0 AMR0 (R/W) 3D16 XXXXXXXX 3D17 XXXXXXXX CAN1 3D18 XXXXXXXX...
Page 722: Appendix B Instructions
APPENDIX APPENDIX B Instructions MB90930 Series APPENDIX B Instructions APPENDIX B describes the instructions used by the F MC-16LX. B.1 Instruction Types B.2 Addressing B.3 Direct Addressing B.4 Indirect Addressing B.5 Execution Cycle Count B.6 Effective address field B.7 How to Read the Instruction List B.8 F2MC-16LX Instruction List...
Page 723: Instruction Types
APPENDIX APPENDIX B Instructions MB90930 Series Instruction Types The F MC-16LX supports 351 types of instructions. Addressing is enabled by using an effective address field of each instruction or using the instruction code itself. ■ Instruction Types The F MC-16LX supports the following 351 types of instructions: •...
Page 724: Addressing
APPENDIX APPENDIX B Instructions MB90930 Series Addressing With the F MC-16LX, the address format is determined by the instruction effective address field or the instruction code itself (implied). When the address format is determined by the instruction code itself, specify an address in accordance with the instruction code used.
Page 725 APPENDIX APPENDIX B Instructions MB90930 Series ■ Effective Address Field Table B.2-1 lists the address formats specified by the effective address field. Table B.2-1 Effective Address Field Code Representation Address format Default bank (RL0) Register direct: Individual parts correspond to the...
Page 726: Direct Addressing
APPENDIX APPENDIX B Instructions MB90930 Series Direct Addressing An operand value, register, or address is specified explicitly in direct addressing mode. ■ Direct Addressing ● Immediate addressing (#imm) Specify an operand value explicitly (#imm4/ #imm8/ #imm16/ #imm32). Figure B.3-1 Example of Immediate Addressing (#imm) MOVW A, #01212H (This instruction stores the operand value in A.)
Page 727 APPENDIX APPENDIX B Instructions MB90930 Series Figure B.3-2 Example of Register Direct Addressing MOV R0, A (This instruction transfers the eight low-order bits of A to the general- purpose register R0.) Before execution A 0 7 1 6 2 5 3 4...
Page 728 APPENDIX APPENDIX B Instructions MB90930 Series ● Physical direct branch addressing (addr24) Specify an offset explicitly for the branch destination address. The size of the offset is 24 bits. Physical direct branch addressing is used for unconditional branch, subroutine call, or software interrupt instruction.
Page 729 APPENDIX APPENDIX B Instructions MB90930 Series ● Abbreviated direct addressing (dir) Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register (DTB).
Page 730 APPENDIX APPENDIX B Instructions MB90930 Series ● I/O direct bit addressing (io:bp) Specify bits in physical addresses 000000 to 0000FF explicitly. Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB).
Page 731 APPENDIX APPENDIX B Instructions MB90930 Series ● Vector Addressing (#vct) Specify vector data in an operand to indicate the branch destination address. There are two sizes for vector numbers: 4 bits and 8 bits. Vector addressing is used for a subroutine call or software interrupt instruction.
Page 732: Indirect Addressing
APPENDIX APPENDIX B Instructions MB90930 Series Indirect Addressing In indirect addressing mode, an address is specified indirectly by the address data of an operand. ■ Indirect Addressing ● Register indirect addressing (@RWj j = 0 to 3) Memory is accessed using the contents of general-purpose register RWj as an address. Address...
Page 733 APPENDIX APPENDIX B Instructions MB90930 Series Figure B.4-2 Example of Register Indirect Addressing with Post Increment (@RWj+ j = 0 to 3) MOVW A, @RW1+ (This instruction reads data by register indirect addressing with post increment and stores it in A.)
Page 734 APPENDIX APPENDIX B Instructions MB90930 Series ● Long register indirect addressing with offset (@RLi + disp8 i = 0 to 3) Memory is accessed using the address that is the 24 low-order bits obtained by adding an offset to the contents of general-purpose register RLi. The offset is 8-bits long and is added as a signed numeric value.
Page 735 APPENDIX APPENDIX B Instructions MB90930 Series ● Register indirect addressing with base index (@RW0 + RW7, @RW1 + RW7) Memory is accessed using the address determined by adding RW0 or RW1 to the contents of general-purpose register RW7. Address bits 16 to 23 are indicated by the data bank register (DTB).
Page 736 APPENDIX APPENDIX B Instructions MB90930 Series ● Program counter relative branch addressing (rel) The address of the branch destination is a value determined by adding an 8-bit offset to the program counter (PC) value. If the result of addition exceeds 16 bits, bank register incrementing or decrementing is not performed and the excess part is ignored, and therefore the address is contained within a 64-kilobyte bank.
Page 737 APPENDIX APPENDIX B Instructions MB90930 Series Figure B.4-9 Example of Register List (rlst) POPW RW0, RW4 (This instruction transfers memory data indicated by the SP to multiple word registers indicated by the register list.) 3 4 F A 3 4 F E ×...
Page 738 APPENDIX APPENDIX B Instructions MB90930 Series ● Accumulator indirect branch addressing (@A) The address of the branch destination is the content (16 bits) of the low-order bytes (AL) of the accumulator. It indicates the branch destination in the bank address space. Address bits 16 to 23 are specified by the program counter bank register (PCB).
Page 739 APPENDIX APPENDIX B Instructions MB90930 Series ● Indirect specification branch addressing (@eam) The address of the branch destination is the word data at the address indicated by eam. Figure B.4-13 Example of Indirect Specification Branch Addressing (@eam) JMP @RW0 (This instruction causes an unconditional branch by register indirect addressing.)
Page 740: Execution Cycle Count
APPENDIX APPENDIX B Instructions MB90930 Series Execution Cycle Count The number of cycles required for instruction execution (execution cycle count) is obtained by adding the number of cycles required for each instruction, "correction value" determined by the condition, and the number of cycles for instruction fetch.
Page 741 APPENDIX APPENDIX B Instructions MB90930 Series ■ Calculating the Execution Cycle Count Table B.5-1 lists execution cycle counts and Table B.5-2 and Table B.5-3 summarize correction value data. Table B.5-1 Execution Cycle Counts in Each Addressing Mode Register access count in...
Page 742 APPENDIX APPENDIX B Instructions MB90930 Series Table B.5-2 Cycle Count Correction Values for Counting Execution Cycles (b) byte (c) word (d) long Operand Cycle Access Cycle Access Cycle Access count count count count count count Internal register Internal memory Even address...
Page 743: Effective Address Field
APPENDIX APPENDIX B Instructions MB90930 Series Effective address field Table B.6-1 shows the effective address field. ■ Effective Address Field Table B.6-1 Effective Address Field Byte count of extended Code Representation Address format address part (RL0) Register direct: Individual parts correspond to...
Page 744: How To Read The Instruction List
APPENDIX APPENDIX B Instructions MB90930 Series How to Read the Instruction List Table B.7-1 describes the items used in "B.8 F2MC-16LX Instruction List", and Table B.7-2 describes the symbols used in the same list. ■ Description of Instruction Presentation Items and Symbols Table B.7-1 Description of Items in the Instruction List (1/2)
Page 745 APPENDIX APPENDIX B Instructions MB90930 Series Table B.7-1 Description of Items in the Instruction List (1/2) Item Description Indicates whether the instruction is a Read Modify Write instruction (reading data from memory by the I instruction and writing the result to memory).
Page 746 APPENDIX APPENDIX B Instructions MB90930 Series Table B.7-2 Explanation on Symbols in the Instruction List (1/2) Symbol Explanation I/O area (000000 to 0000FF #imm4 4-bit immediate data #imm8 8-bit immediate data #imm16 16-bit immediate data #imm32 32-bit immediate data ext (imm8)
Page 747: F 2 Mc-16Lx Instruction List
APPENDIX APPENDIX B Instructions MB90930 Series MC-16LX Instruction List Table B.8-1 to Table B.8-18 list the instructions used by the F MC-16LX. ■ F MC-16LX Instruction List Table B.8-1 41 Transfer Instructions (Byte) Mnemonic Operation C RMW byte (A) ← (dir) A,dir byte (A) ←...
Page 748 APPENDIX APPENDIX B Instructions MB90930 Series Table B.8-2 38 Transfer Instructions (Word, Long Word) Mnemonic Operation C RMW word (A) ← (dir) MOVW A,dir word (A) ← (addr16) MOVW A,addr16 word (A) ← (SP) MOVW A,SP word (A) ← (RWi) MOVW A,RWi word (A) ←...
Page 749 APPENDIX APPENDIX B Instructions MB90930 Series Table B.8-3 42 Addition/Subtraction Instructions (Byte, Word, Long Word) Mnemonic Operation C RMW byte (A) ← (A) + imm8 A,#imm8 byte (A) ← (A) + (dir) A,dir byte (A) ← (A) + (ear) A,ear byte (A) ←...
Page 750 APPENDIX APPENDIX B Instructions MB90930 Series Table B.8-4 12 Increment/decrement Instructions (Byte, Word, Long Word) Mnemonic Operation C RMW byte (ear) ← (ear) + 1 2 × (b) byte (eam) ← (eam) + 1 5+(a) byte (ear) ← (ear) - 1 2 ×...
Page 751 APPENDIX APPENDIX B Instructions MB90930 Series Table B.8-6 11 Unsigned Multiplication/Division Instructions (Word, Long Word) Mnemonic Operation C RMW DIVU word (AH) / byte (AL) quotient → byte (AL) remainder → byte (AH) DIVU A,ear word (A) / byte (ear) quotient →...
Page 752 APPENDIX APPENDIX B Instructions MB90930 Series Table B.8-7 11 Signed Multiplication/Division Instructions (Word, Long Word) Mnemonic Operation C RMW word (AH) / byte (AL) quotient → byte (AL) remainder → byte (AH) A,ear word (A) / byte (ear) quotient → byte (A) remainder → byte (ear)
Page 753 APPENDIX APPENDIX B Instructions MB90930 Series Table B.8-8 39 Logic 1 Instructions (Byte, Word) Mnemonic Operation C RMW byte (A) ← (A) and imm8 A,#imm8 byte (A) ← (A) and (ear) A,ear byte (A) ← (A) and (eam) A,eam 4+(a) byte (ear) ←...
Page 754 APPENDIX APPENDIX B Instructions MB90930 Series Table B.8-9 6 Logic 2 Instructions (Long Word) Mnemonic Operation C RMW long (A) ← (A) and (ear) ANDL A,ear long (A) ← (A) and (eam) ANDL A,eam 7+(a) long (A) ← (A) or (ear) A,ear long (A) ←...
Page 755 APPENDIX APPENDIX B Instructions MB90930 Series Table B.8-12 18 Shift Instructions (Byte, Word, Long Word) Mnemonic Operation C RMW byte (A) ← Right rotation with carry RORC byte (A) ← Right rotation with carry ROLC byte (ear) ← Right rotation with carry RORC 2 ×...
Page 756 APPENDIX APPENDIX B Instructions MB90930 Series Table B.8-13 31 Branch 1 Instructions Mnemonic Operation C RMW Branch on (Z) = 1 BNZ/ Branch on (Z) = 0 Branch on (C) = 1 BNC/ Branch on (C) = 0 Branch on (N) = 1...
Page 757 APPENDIX APPENDIX B Instructions MB90930 Series Table B.8-14 19 Branch 2 Instructions Mnemonic Operation I S T N Z V C RMW CBNE A,#imm8,rel Branch on byte (A) not equal to imm8 - * * * * CWBNE A,#imm16,rel Branch on word (A) not equal to imm16...
Page 758 APPENDIX APPENDIX B Instructions MB90930 Series Table B.8-15 28 Other Control Instructions (Byte, Word, Long Word) Mnemonic Operation C RMW word (SP) ← (SP) - 2, ((SP)) ← (A) PUSHW word (SP) ← (SP) - 2, ((SP)) ← (AH) PUSHW word (SP) ←...
Page 759 APPENDIX APPENDIX B Instructions MB90930 Series Table B.8-16 21 Bit Operand Instructions Mnemonic Operation C RMW byte (A) ← (dir:bp)b MOVB A,dir:bp byte (A) ← (addr16:bp)b MOVB A,addr16:bp byte (A) ← (io:bp)b MOVB A,io:bp 2 × (b) bit (dir:bp)b ← (A) MOVB dir:bp,A 2 ×...
Page 760 APPENDIX APPENDIX B Instructions MB90930 Series Table B.8-18 10 String Instructions Mnemonic Operation C RMW byte transfer @AH+ ← @AL+, counter = RW0 - MOVS / MOVSI byte transfer @AH- ← @AL-, counter = RW0 MOVSD byte search @AH+ ← AL, counter = RW0 SCEQ / SCEQI byte search @AH- ←...
Page 761: Instruction Map
APPENDIX APPENDIX B Instructions MB90930 Series Instruction Map Each F MC-16LX instruction code consists of 1 or 2 bytes. Therefore, the instruction map consists of multiple pages. Table B.9-2 to Table B.9-21 summarize the F MC-16LX instruction map. ■ Structure of Instruction Map Figure B.9-1 Structure of Instruction Map...
Page 762 APPENDIX APPENDIX B Instructions MB90930 Series Figure B.9-2 Correspondence between Actual Instruction Code and Instruction Map Some instructions do not contain byte 2. Length varies depending on the instruction. Instruction . . . Byte 1 Byte 2 Operand Operand code...
Page 763 APPENDIX APPENDIX B Instructions MB90930 Series Table B.9-2 Basic Page Map CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 764 APPENDIX APPENDIX B Instructions MB90930 Series Table B.9-3 Bit Operation Instruction Map (First Byte = 6C FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 765 APPENDIX APPENDIX B Instructions MB90930 Series Table B.9-4 Character String Operation Instruction Map (First Byte = 6E CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 766 APPENDIX APPENDIX B Instructions MB90930 Series Table B.9-5 2-byte Instruction Map (First Byte = 6F FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 767 APPENDIX APPENDIX B Instructions MB90930 Series Table B.9-6 ea Instruction 1 (First Byte = 70 CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 768 APPENDIX APPENDIX B Instructions MB90930 Series Table B.9-7 ea Instruction 2 (First Byte = 71 FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 769 APPENDIX APPENDIX B Instructions MB90930 Series Table B.9-8 ea Instruction 3 (First Byte = 72 CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 770 APPENDIX APPENDIX B Instructions MB90930 Series Table B.9-9 ea Instruction 4 (First Byte = 73 FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 771 APPENDIX APPENDIX B Instructions MB90930 Series Table B.9-10 ea Instruction 5 (First Byte = 74 CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 772 APPENDIX APPENDIX B Instructions MB90930 Series Table B.9-11 ea Instruction 6 (First Byte = 75 FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 773 APPENDIX APPENDIX B Instructions MB90930 Series Table B.9-12 ea Instruction 7 (First Byte = 76 CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 774 APPENDIX APPENDIX B Instructions MB90930 Series Table B.9-13 ea Instruction 8 (First Byte = 77 FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 775 APPENDIX APPENDIX B Instructions MB90930 Series Table B.9-14 ea Instruction 9 (First Byte = 78 CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 776 APPENDIX APPENDIX B Instructions MB90930 Series Table B.9-15 MOVEA RWi, ea Instruction (First Byte = 79 FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 777 APPENDIX APPENDIX B Instructions MB90930 Series Table B.9-16 MOV Ri, ea Instruction (First Byte = 7A CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 778 APPENDIX APPENDIX B Instructions MB90930 Series Table B.9-17 MOVW RWi, ea Instruction (First Byte = 7B FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 779 APPENDIX APPENDIX B Instructions MB90930 Series Table B.9-18 MOV ea, Ri Instruction (First Byte = 7C CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 780 APPENDIX APPENDIX B Instructions MB90930 Series Table B.9-19 MOVW ea, Rwi Instruction (First Byte = 7D FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 781 APPENDIX APPENDIX B Instructions MB90930 Series Table B.9-20 XCH Ri, ea Instruction (First Byte = 7E CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 782 APPENDIX APPENDIX B Instructions MB90930 Series Table B.9-21 XCHW RWi, ea Instruction (First Byte = 7F FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 783: Index
INDEX MB90930 Series INDEX The index follows on the next page. This is listed in alphabetic order. CM44-10150-1E FUJITSU MICROELECTRONICS LIMITED...
Page 784 INDEX MB90930 Series Index OS Function of 16-bit Reload Timer..320 Numerics Interrupts and EI OS of 16-bit 1/2 Bias Reload Timer ...... 308, 320 1/2 Bias,1/2 Duty Output Waveform ...576 Interrupts of 16-bit Reload Timer....320 1/2 Duty Notes on Using 16-bit Reload Timer ..329 1/2 Bias,1/2 Duty Output Waveform ...576...
Page 785 INDEX MB90930 Series Bank Registers (PCB,DTB,USB,SSB,ADB) ... 52 Accumulator (A).........41 Bank Select Prefix A/D Control Status Register (PCB,DTB,ADB,SPB)....55 Lower Bits in the A/D Control Status Register ADCR (ADCS0)........401 A/D Data Registers (ADCR0/ADCR1)..403 Upper Bits in the A/D Control Status Register ADCS (ADCS1)........397...
Page 786 INDEX MB90930 Series Asynchronous Mode Bit Configuration of Extended Communication Operation in Asynchronous Mode ....466 Control Register (ECCR) ..... 447 Automatic Algorithm Bit Configuration of Extended Status Control Register (ESCR)......445 Automatic Algorithm Termination Timing ........627 Bit Configuration of ID Register x (x = 0 to 15) (IDRx) ........
Page 787 INDEX MB90930 Series Bit Timing Pin Block Diagram for Port 8 ....224 Pin Block Diagram for Port 9 ....230 Setting Bit Timing........540 Pin Block Diagram for Port C....236 Bit Timing Register Pin Block Diagram for Port D....243 Bit Configuration of Bit Timing Register Pin Block Diagram for Port E ....
Page 788 INDEX MB90930 Series Clock Selection Register Pins Used for CAN WAKE UP Clock Selection Register (CKSCR) .... 124 Function........547 Clock Supply Map Condition Code Register (PS:CCR) ....47 Clock Supply Map........120 Chip Chip/Sector Erase ........635 Common Register Bank Prefix (CMR) ..56...
Page 789 INDEX MB90930 Series Count Current Consumption Count Operation ........307 CPU Operation Modes and Current Consumption....138 Counter Operation Counter Operation States ......322 CPCLR Compare Clear Register (CPCLR) ....296 Data Counter Data Counter (DCT) ........87 Bit Configuration of the Low-voltage/CPU...
Page 790 INDEX MB90930 Series DLC Register 1/3 Bias,1/3 Duty Output Waveform ..579 1/3 Bias,1/4 Duty Output Waveform ..582 Bit Configuration of DLC Register x (x = 0 to 15) (DLCRx)........530 Example of LCD Panel Connection and Display Data (1/2 Duty Drive Method) ..578...
Page 791 INDEX MB90930 Series Extended Intelligent I/O Service Processing Procedure for Extended Intelligent OS) .......90 I/O Service (EI Configuration of Extended Intelligent I/O Processing Time for Extended Intelligent I/O OS) Descriptor Service (EI (ISD)..........86 Service (EI OS) (Time Consumed per Transfer) ........93...
Page 792 (SGFR0/SGFR1) ......615 Flag (DQ5) ........637 Fujitsu Standard Flag Change Suppress Prefix Flag Change Suppress Prefix (NCC) .....57 Pins Used for Fujitsu Standard Serial On-board Writing........651 Flash Memory Erasing All Data of Flash Memory (Chip Erase) ........643 Flash Memory Write Control Registers (FWR0/FWR1) ......
Page 793 INDEX MB90930 Series High-current Output Buffer Input Capture Block Diagram of Input Capture ....283 Handling of Power Supply for High-current Configuration of Input Capture ....282 Output Buffer Pins (DVCC, DVSS) ......23 Input Capture Input Select Register (ICISR) ........290 OS....
Page 794 INDEX MB90930 Series Interrupt Timing of Reception Interrupt Generation and Flag Set ........453 Example of Multiple Interrupts.....80 Example Program for Interrupt Handling..98 Timing of Transmission Interrupt Generation and Flag Set ........ 455 Exception Handling Interrupt by Execution of Undefined Instruction .....95 Transition to Standby Mode and External Interrupt Function ......380...
Page 795 INDEX MB90930 Series Linear Addressing Example of LCD Panel Connection and Display Linear Addressing and Bank Addressing ..32 Data (1/2 Duty Drive Method)..578 Example of LCD Panel Connection and Display LIN-UART Data (1/3 Duty Drive Method)..581 Block Diagram of LIN-UART ....430 Block Diagram of LIN-UART Pins....
Page 796 Rating Operation in Asynchronous LIN Mode..473 (for Latch-up Prevention)....21 MB90930 Series Operation in Asynchronous Mode....466 Overview of MB90930 Series ......2 Operation in Internal Clock Mode (Reload Mode) ......323 Operation in Synchronous Mode (Operation Continuous Conversion Mode Mode 2)........470 ) ...411...
Page 797 INDEX MB90930 Series Multi-byte Operation States in the Low-power Consumption Mode ..........160 Allocating Multi-byte Data in RAM..... 36 Allocating Multi-byte Data on the Stack ..37 Operation States in the Standby Mode..147 Allocating Multi-byte Operand ....36 Operations and Applications of Continuous Multi-level Message Buffer Conversion Mode......416...
Page 798 INDEX MB90930 Series Output Driver PLL/Sub Clock Control Register Output Driver Driving Power Supply for PLL/Sub Clock Control Register Port 7 ..........221 (PSCCR) ........128 Output Driver Driving Power Supply for Port 0 Port 8 ..........228 Functions of Port 0 Registers..... 181 Overview Operation of Port 0 ........
Page 799 INDEX MB90930 Series Processing of Power Supply Pins ....22 Output Driver Driving Power Supply for Port 7 ..........221 Power-on Pin Block Diagram for Port 7 .....217 Power-on Sequence for A/D Converter Power Supply and Analog Input....23 Port 7 Configuration........215 Voltage Start Up Time at Power-on....
Page 800 INDEX MB90930 Series Interrupt Level Mask Register (PS:ILM) ..49 Receive Interrupt Enable Register Register Bank Pointer (PS:RP) .....48 Bit Configuration of Receive Interrupt Enable Register (RIER) ......520 PSCCR Receive Message PLL/Sub Clock Control Register (PSCCR) ........128 Storing the Receive Message ..... 536...
Page 801 INDEX MB90930 Series Bit Configuration of ID Register x (x = 0 to 15) Configuration of Interrupt Control Register (IDRx) ........526 (ICR) ........... 69 Bit Configuration of IDE Register Decrement Grade Registers (SGDR0/SGDR1)......617 (IDER)........510 Direct Page Register (DPR)......51 Bit Configuration of Last Event Indication Register (LEIR) ......503...
Page 802 INDEX MB90930 Series Sample Setting of the ID Register ....527 Reset Serial Control Register (SCR) ....437 Bit Configuration of the Low-voltage/CPU Serial Status Register (SSR) .......441 Operation Detection Reset Control Register (LVRC) ......590 Setup Flowchart for Flash Memory Write Block Diagram of External Reset Pin ..
Page 803 Bit Configuration of Remote Request Receive Serial Control Register (SCR)....437 Register (RRTRR) .......518 Serial On-board Writing RTEC Pins Used for Fujitsu Standard Serial On-board Bit Configuration of Receive and Transmit Error Writing........651 Counters (RTEC) ......505 Serial Programming Connection...
Page 804 INDEX MB90930 Series SGCRH Reset Source Bit........112 Reset Sources........... 104 Bit Configuration of Sound Control Register (SGCRH0/SGCRH1, Reset Sources and Oscillation Stabilization Wait Time .......... 107 SGCRL0/SGCRL1)......613 State of Reset Source Bits ......114 SGCRL Bit Configuration of Sound Control Register...
Page 805 INDEX MB90930 Series Stop Conversion Mode Transmission Data Register (TDR) .... 444 TIER Operations and Applications of Stop Conversion Mode ..........417 Bit Configuration of Transmission Interrupt Setup for Stop Conversion Mode ....417 Enable Register (TIER)....516 Stop Conversion Mode Time-base Timer ) ...411...
Page 806 INDEX MB90930 Series Transition Notes Accessing Low-power UART Consumption Mode Control Register UART Baud Rate Selection....... 457 (LPMCR) for the Transition to the Undefined Instruction Standby Mode ......165 Exception Handling Interrupt by Execution of Notes on Transition to Standby Mode ..163 Undefined Instruction ....
Page 807 INDEX MB90930 Series Watchdog Timer Control Register Note on Setting the FMCS:WE Bit..... 632 Bit Configuration of the Watchdog Timer Control Register (WDTC).....261 Write Waveform How to Write/Erase Flash Memory .... 624 1/2 Bias,1/2 Duty Output Waveform ...576 Write............635 1/3 Bias,1/3 Duty Output Waveform ...579...
Page 808 INDEX MB90930 Series FUJITSU MICROELECTRONICS LIMITED CM44-10150-1E...
Page 809 CM44-10150-1E FUJITSU MICROELECTRONICS • CONTROLLER MANUAL MC-16LX 16-BIT MICROCONTROLLER MB90930 Series HARDWARE MANUAL August 2009 the first edition FUJITSU MICROELECTRONICS LIMITED Published Sales Promotion Dept. Edited...

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