Configuration Of Address Match Detection Function - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION

24.3 Configuration of Address Match Detection Function

This section details the registers used by the address match detection function.
I List of Registers and Reset Values of Address Match Detection Function
Figure 24.3-1 List of Registers and Reset Values of Address Match Detection Function
Address detection control register (PACSR)
Detect address setting register 0 (PADR0)
: High
Detect address setting register 0 (PADR0)
: Middle
Detect address setting register 0 (PADR0)
: Low
Detect address setting register 1 (PADR1)
: High
Detect address setting register 1 (PADR1)
: Middle
Detect address setting register 1 (PADR1)
: Low
×
: Undefined
452
bit 7 6 5 4
0 0 0 0
bit 7 6 5 4
× × × ×
bit 15 14 13 12
× × × ×
bit 7 6 5 4
× × × ×
bit 7 6 5 4
× × × ×
bit 15 14 13 12
× × × ×
bit 7 6 5 4
× × × ×
3 2 1 0
0 0 0 0
3 2 1 0
× × × ×
11 10 9 8
× × × ×
3 2 1 0
× × × ×
3 2 1 0
× × × ×
11 10 9 8
× × × ×
3 2 1 0
× × × ×