Overview Of The Watchdog Timer - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 9 WATCHDOG TIMER
9.1

Overview of the Watchdog Timer

The watchdog timer consists of the 2-bit watchdog counter which uses a carry signal
of the 18-bit time-based timer as a clock source, the control register, and the watchdog
reset control section.
■ Watchdog Timer Register
Watchdog control register
Address:0000A8
Read/write
Initial value
■ Watchdog Timer Block Diagram
TBTC
TBC1
TBC0
TBR
TBIE
TBOF
Time-base
interrupt
WDTC
WT1
WT0
WTE
PONR
STBR
WRST
ERST
SRST
154
Figure 9.1-1 Watchdog Timer Register
7 6
bit
PONR STBR WRST ERST SRST
H
(R) (R) (R)
(X) (X) (X)
Figure 9.1-2 Watchdog Timer Block Diagram
2
2
Selector
2
2
TBTRES
AND
2-bit counter
Selector
CLR
5 4 2
3
WTE
(R) (R) (W)
(X) (X) (1)
Clock input
12
14
16 Time-based timer
19
12 14
2 2 2
Watchdog reset
generation circuit
OF
CLR
1 0
WT1 WT0 WDTC
(W) (W)
(1) (1)
Oscillation clock
16 19
2
WDGRST
To the WDGRST internal
reset generation circuit
From power-on
generation
From the hardware
standby control circuit
RST pin
From the RST bit of
the LPMCR register