Figure 6.2 Block Diagram Of Watchdog Timer - Fujitsu F2MC-8L MB89620 Series Hardware Manual

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6. Block Diagram of Watchdog Timer
The watchdog timer consists of the following four blocks:
• Watchdog timer counter
• Reset controller
• Counter clear controller
• Watchdog timer control register (WDTC)
n Block Diagram of Watchdog Timer
— —
Sleep mode start
Hold state start
F : Source oscillation
C
l Watchdog timer counter (1-bit counter)
A 1-bit counter that uses the 2
l Reset controller
Generates a reset signal to the CPU when an overflow occurs on the watchdog timer counter.
l Counter clear controller
Controls clearing and halting the operation of the watchdog timer counter.
l WDTC register
The WDTC register is used to activate or clear the watchdog timer counter.
As the register is write-only, the bit manipulation instructions cannot be used.
MB89620 series
WDTC register
— — WTE3 WTE2 WTE1 WTE0
Counter clear
controller
(Timebase timer counter)
Divide-by-two
F ×2 ×2
C
1 2 . . .
Clear (stop mode start)

Figure 6.2 Block Diagram of Watchdog Timer

20
bits of the timebase timer as a count clock
Watchdog timer
CLR
Activate
Overflow
1-bit counter
×2 ×2 ×2 ×2 ×2
10 11 12 13 14
CHAPTER 6 WATCHDOG TIMER
Reset controller
×2 ×2 ×2 ×2 ×2
15 16 17 18 19
RST
×2
20
131