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• Vector number—This 8-bit field, vector[7–0], defines the exception type. It is
calculated by the processor for internal faults and is supplied by the peripheral for
interrupts. See Table 2-18.
2.8.2 Processor Exceptions
Table 2-21 describes MCF5272 exceptions.
Exception
Access Error
Caused by an error when accessing memory. For an access error on an instruction fetch, the
processor postpones the error reporting until the instruction at the faulted reference is executed.
Thus, faults that occur during instruction prefetches that are followed by a change of instruction flow
do not generate an exception. When the processor attempts to execute an instruction with a faulted
opword or extension word, the access error is signaled, and the instruction is aborted. For this type of
exception, the programming model is not altered by the faulted instruction.
If an access error occurs on an operand read, the processor immediately aborts the current
instruction execution and initiates exception processing. In this case, any address register changes
caused by the auto-addressing modes, (An)+ and -(An), have already occurred. In addition, if an
access error occurs during the execution of a MOVEM instruction loading from memory, registers
updated before the fault occurs contain the memory operand.
Due to the processor pipeline implementation, a write cycle may be decoupled from the execution of
the instruction causing the write. Thus, if an access error occurs on an operand write, the signaling of
the error is imprecise. Accordingly, the PC contained in the exception stack frame represents the
location in the program when the access error is signaled, not necessarily the instruction causing the
fault. All programming model updates associated with the write instruction are complete. The NOP
instruction can be used to help identify write access errors. A NOP is not executed until all previous
operations, including any pending writes are complete. Thus if any previous write terminates with an
access error, it is guaranteed to be reported on the NOP.
Address
Caused by an attempted execution transferring control to an odd instruction address (that is, if bit 0 of
Error
the target address is set), an attempted use of a word-sized index register (Xi.w) or a scale factor of
8 on an indexed effective addressing mode, or attempted execution of an instruction with a full-format
indexed addressing mode.
Illegal
On Version 2 ColdFire implementations, only some illegal opcodes (0x0000 and 0x4AFC) are
Instruction
decoded and generate an illegal instruction exception. Additionally, attempting to execute an illegal
line A or line F opcode generates unique exception types: vectors 10 and 11, respectively. If any
other nonsupported opcode is executed, the resulting operation is undefined.
ColdFire processors do not provide illegal instruction detection on extension words of any instruction,
including MOVEC. Attempting to execute an instruction with an illegal extension word causes
undefined results.
Divide by
Attempted division by zero causes an exception (vector 5, offset = 0x014) except when the PC points
Zero
to the faulting instruction (DIVU, DIVS, REMU, REMS).
Privilege
Caused by attempted execution of a supervisor mode instruction while in user mode. The ColdFire
Violation
Programmer's Reference Manual lists supervisor- and user-mode instructions.
272
Table 2-21. MCF5
Description
Chapter 2. ColdFire Core
Exception Processing Overview
Exceptions
2-39
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