8.2.14 Bit Field Manipulation Instructions
The bit field manipulation instructions table indicates the number of clock periods needed
for the processor to perform the specified bit field operation using the given addressing
mode. Footnotes indicate when it is necessary to add another table entry to calculate the
total effective execution time for the instruction. The total number of clock cycles is outside
the parentheses; the number of read, prefetch, and write cycles is given inside the
parentheses as (r/p/w). These cycles are included in the total clock cycle number.
Instruction
BFTST
‡
BFTST
‡
BFTST
BFCHG
‡
BFCHG
‡
BFCHG
BFCLR
‡
BFCLR
‡
BFCLR
BFSET
‡
BFSET
‡
BFSET
BFEXTS
‡
BFEXTS
‡
BFEXTS
BFEXTU
‡
BFEXTU
‡
BFEXTU
BFINS
‡
BFINS
‡
BFINS
BFFFO
‡
BFFFO
‡
BFFFO
‡Add Calculate Immediate Address Time
NOTE: A bit field of 32 bits may span five bytes that require two operand cycles to access or may span four bytes that
require only one operand cycle to access.
8-36
Dn
Mem (< 5 Bytes)
Mem (5 Bytes)
Dn
Mem (< 5 Bytes)
Mem (5 Bytes)
Dn
Mem (< 5 Bytes)
Mem (5 Bytes)
Dn
Mem (< 5 Bytes)
Mem (5 Bytes)
Dn
Mem (< 5 Bytes)
Mem (5 Bytes)
Dn
Mem (< 5 Bytes)
Mem (5 Bytes)
Dn
Mem (< 5 Bytes)
Mem (5 Bytes)
Dn
Mem (< 5 Bytes)
Mem (5 Bytes)
M68020 USER'S MANUAL
Best Case
Cache Case
3(0/0/0)
6(0/0/0)
11(1/0/0)
11(1/0/0)
15(2/0/0)
15(2/0/0)
9(0/0/0)
12(0/0/0)
16(1/0/1)
16(1/0/1)
24(2/0/2)
24(2/0/2)
9(0/0/0)
12(0/0/0)
16(1/0/1)
16(1/0/1)
24(2/0/2)
24(2/0/2)
9(0/0/0)
12(0/0/0)
16(1/0/1)
16(1/0/1)
24(2/0/2)
24(2/0/2)
5(0/0/0)
8(0/0/0)
13(1/0/0)
13(1/0/0)
18(2/0/0)
18(2/0/0)
5(0/0/0)
8(0/0/0)
13(1/0/0)
13(1/0/0)
18(2/0/0)
18(2/0/0)
7(0/0/0)
10(0/0/0)
14(1/0/1)
14(1/0/1)
20(2/0/2)
20(2/0/2)
15(0/0/0)
18(0/0/0)
24(1/0/0)
24(1/0/0)
32(2/0/0)
32(2/0/0)
Worst Case
7(0/1/0)
12(1/1/0)
16(2/1/0)
12(0/1/0)
16(1/1/1)
24(2/1/2)
12(0/1/0)
16(1/1/1)
24(2/1/2)
12(0/1/0)
16(1/1/1)
24(2/1/2)
8(0/1/0)
13(1/1/0)
18(2/1/0)
8(0/1/0)
13(1/1/0)
18(2/1/0)
10(0/1/0)
15(1/1/1)
21(2/1/2)
18(0/1/0)
24(1/1/0)
32(2/1/0)
MOTOROLA