Figure 7-4 Illegal Instruction Interrupt Servicing; Interrupt Arbitration - Motorola DSP56800 Manual

Interrupts and the Processing States
Interrupt Control Cycle 1
Interrupt Control Cycle 2
Fetch
Decode
Execute
Instruction Cycle Count
i = Interrupt
ii = Interrupt Instruction Word
II = Illegal Instruction
n = Normal Instruction Word
This interrupt can be used as a diagnostic tool to allow the programmer to examine the stack and locate the
illegal instruction, or the application program can be restarted with the hope that the failure was a soft
error. The ILLEGAL instruction, found in Appendix A, "Instruction Set Details," is useful for testing the
illegal interrupt service routine to verify that it can recover correctly from an illegal instruction. Note that
the illegal instruction trap does not fire for all invalid opcodes.
7.3.6

Interrupt Arbitration

Interrupt arbitration and control, which occurs concurrently with the fetch-decode-execute cycle, takes two
instruction cycles. External interrupts are internally synchronized with the processor clock before their
interrupt-pending flags are set. Each external and internal interrupt has its own flag. After each instruction
is executed, the DSP arbitrates all interrupts. During arbitration, each pending interrupt's IPL is compared
with the interrupt mask in the SR, and the interrupt is either allowed or disallowed. The remaining pending
7-12
Main
Program
Fetches
II (NOP)
n6
No Fetch
No Fetch
(a) Instruction Fetches from Memory
n1 n2 n3
n1 n2
n1
1 2 3 4
(b) Program Controller Pipeline
Figure 7-4. Illegal Instruction Interrupt Servicing
DSP56800 Family Manual
Interrupt
Service Routine
Fetches
Illegal Instruction Interrupt
Recognized as Pending
i
i
n4 II n6 — —
n3 n4 II — —
n2 n3 n4 NOP —
5 6 7 8 9
I1
I2
I3
I4
I5
ii1 ii2 ii3 ii4 ii5
— ii1 ii2 ii3 ii4
— — ii1 ii2 ii3
10 11 12 13 14
AA0059