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correspond to direct-store (T
=
1) segments. Furthermore, Rand C bits are maintained only
for accesses made while address translation is enabled (MSR[IR]
=
1 or MSR[DR]
=
1).
In the MPC750, the referenced and changed bits are updated as follows:
•
For TLB hits, the C bit is updated according to Table 5-7.
•
For TLB misses, when a table search operation is in progress to locate a PTE. The
Rand C bits are updated (set, if required) to reflect the status of the page based on
this access.
Table
5-7.
Table Search Operations to Update History Bits-TLB Hit Case
Rand C bits
Processor Action
inTLB Entry
00
Combination doesn't occur
01
Combination doesn't occur
10
Read: No special action
Write: The MPC750 initiates a table search operation to update C.
11
No special action for read or write
The table shows that the status of the C bit in the TLB entry (in the case of a TLB hit) is
what causes the processor to update the C bit in the PTE (the R bit is assumed to be set in
the page tables if there is a TLB hit). Therefore, when software clears the R and C bits in
the page tables in memory, it must invalidate the TLB entries associated with the pages
whose referenced and changed bits were cleared.
The debt and debtst instructions can execute if there is a TLBIBAT hit or if the processor
is in real addressing mode. In case of a TLB or BAT miss, these instructions are treated as
no-ops; they do not initiate a table search operation and they do not set either the R or C bits.
As defined by the PowerPC architecture, the referenced and changed bits are updated as if
address translation were disabled (real addressing mode). If these update accesses hit in the
data cache, they are not seen on the external bus. If they miss in the data cache, they are
performed as typical cache line fill accesses on bus (assuming the data cache is enabled).
5.4.1.1 Referenced Bit
The referenced (R) bit of a page is located in the PTE in the page table. Every time a page
is referenced (with a read or write access) and the R bit is zero, the MPC750 sets the R bit
in the page table. The OEA specifies that the referenced bit may be set immediately, or the
setting may be delayed until the memory access is determined to be successful. Because the
reference to a page is what causes a PTE to be loaded into the TLB, the referenced bit in all
MPC750 TLB entries is effectively always set. The processor never automatically clears the
referenced bit.
The referenced bit is only a hint to the operating system about the activity of a page. At
times, the referenced bit may be set although the access was not logically required by the
5-22
MPC750 RISC Microprocessor User's Manual
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