Block Diagram - Hitachi SH7750 series Hardware Manual

Superh risc engine
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16.1.2

Block Diagram

Figure 16.1 shows a block diagram of the SCIF.
SCFRDR2
(16-stage)
RxD2
SCRSR2
TxD2
SCK2
CTS2
RTS2
SCRSR2:
Receive shift register
SCFRDR2: Receive FIFO data register
SCTSR2:
Transmit shift register
SCFTDR2: Transmit FIFO data register
SCSMR2:
Serial mode register
SCSCR2:
Serial control register
Module data bus
SCFTDR2
(16-stage)
SCTSR2
Transmission/
reception
Parity generation
Parity check
SCFSR2:
SCBRR2:
SCSPTR2: Serial port register
SCFCR2:
SCFDR2:
SCLSR2:
Figure 16.1 Block Diagram of SCIF
SCBRR2
SCSMR2
SCLSR2
SCFDR2
SCFCR2
SCFSR2
Baud rate
generator
SCSCR2
SCSPTR2
control
Clock
External clock
SCIF
Serial status register
Bit rate register
FIFO control register
FIFO data count register
Line status register
Rev. 4.0, 04/00, page 567 of 850
Internal
data bus
Pφ/4
Pφ/16
Pφ/64
TXI
RXI
ERI
BRI

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