Hitachi SH7750 series Hardware Manual page 312

Bits 8 to 6—Address-2(
time from address output to 2(/:( assertion on the connected PCMCIA interface. The setting of
these bits is selected when the PCMCIA access TC bit is set to 1.
Bit 8: A6TED2
0
1
2(/:( :( Negation-Address Delay (A5TEH2–A5TEH0): These bits set the address
2( 2( :( :(
Bits 5 to 3—2(
hold delay time from 2(/:( negation in a write on the connected PCMCIA interface or in an I/O
card read. The setting of these bits is selected when the PCMCIA access TC bit is cleared to 0.
Bit 5: A5TEH2
0
1
2(/:( 2( 2( :( Assertion Delay (A6TED2–A6TED0): These bits set the delay :( :(
Bit 7: A6TED1
0
1
0
1
Bit 4: A5TEH1
0
1
0
1
Bit 6: A6TED0
0
1
0
1
0
1
0
1
Bit 3: A5TEH0
0
1
0
1
0
1
0
1
Waits Inserted
0 (Initial value)
1
2
3
6
9
12
15
Waits Inserted
0 (Initial value)
1
2
3
6
9
12
15
Rev. 4.0, 04/00, page 301 of 850