Hitachi SH7750 series Hardware Manual page 4

Revisions and Additions in this Edition
Page Item
2 1.1 SH7750 Features
Table 1.1
85 5.3.1 Exception Handling Flow
88 5.5.1 Exception Flow
91 5.5.3 Exception Requests and BL Bit
92 5.6.1 Resets (1) Power-On Reset
97 to 110 5.6.2 General Exceptions
(1) Data TLB Miss Exception to (14) FPU
Exception
111 to 113 5.6.3 Interrupts
(1) NMI to (3) Peripheral Module Interrupts
115 5.7 Usage Notes
2. If an exception or interrupt occurs when
SR.BL = 1, a. Exception
260 13.1.3
Table 13.1 BSC Pins
279 13.2.2
379 to 384 13.3.7 PCMCIA Interface
Figure 13.45 Basic Timing for PCMCIA
Memory Card Interface
Figure 13.46 Wait Timing for PCMCIA
Memory Card Interface
Figure 13.48 Basic Timing for PCMCIA I/O
Card Interface
Figure 13.49 Wait Timing for PCMCIA I/O
Card Interface
Figure 13.50 Dynamic Bus Sizing Timing for
PCMCIA I/O Card Interface
Pin Configuration
Bus Control Register 2 (BCR2)
Revisions (See Manual for Details)
167 MHz and 128 MHz operating
frequency versions added
• R15 added to description
• Save general register 15 (SGR)
added to description
• RTE instruction description added
SGR added to description
Description amended
Description added to Transition
operations
• Description added to Transition
operations
• "SGR = R15;" added to each
program
• Description added to Transition
operations
• "SGR = R15;" added to each
program
Description amended for a. Exception
Modification of data bus (D63—D52,
D31—D0)
Modify D51-D32 to D60-D52
Bits 15 and 14, Area 0 Bus Width
(A0SZ1, A0SZ0)
Table added
DACKn waveform added
Rev. 4.0, 04/00, page vii of 20