Hitachi SH7750 series Hardware Manual page 16

Section 20 User Break Controller (UBC)
20.1 Overview........................................................................................................................... 677
20.1.1 Features................................................................................................................ 677
20.1.2 Block Diagram..................................................................................................... 678
20.2 Register Descriptions ........................................................................................................ 680
20.2.1 Access to UBC Control Registers ........................................................................ 680
20.2.2 Break Address Register A (BARA) ..................................................................... 681
20.2.3 Break ASID Register A (BASRA)....................................................................... 682
20.2.4 Break Address Mask Register A (BAMRA)........................................................ 682
20.2.5 Break Bus Cycle Register A (BBRA).................................................................. 683
20.2.6 Break Address Register B (BARB)...................................................................... 685
20.2.7 Break ASID Register B (BASRB) ....................................................................... 685
20.2.8 Break Address Mask Register B (BAMRB) ........................................................ 685
20.2.9 Break Data Register B (BDRB) ........................................................................... 685
20.2.10 Break Data Mask Register B (BDMRB).............................................................. 686
20.2.11 Break Bus Cycle Register B (BBRB) .................................................................. 687
20.2.12 Break Control Register (BRCR) .......................................................................... 687
20.3 Operation .......................................................................................................................... 689
20.3.1 Explanation of Terms Relating to Accesses......................................................... 689
20.3.2 Explanation of Terms Relating to Instruction Intervals ....................................... 690
20.3.3 User Break Operation Sequence .......................................................................... 691
20.3.4 Instruction Access Cycle Break ........................................................................... 692
20.3.5 Operand Access Cycle Break............................................................................... 693
20.3.6 Condition Match Flag Setting .............................................................................. 694
20.3.7 Program Counter (PC) Value Saved .................................................................... 694
20.3.8 Contiguous A and B Settings for Sequential Conditions ..................................... 695
20.3.9 Usage Notes ......................................................................................................... 696
20.4 User Break Debug Support Function ................................................................................ 697
20.5 Examples of Use ............................................................................................................... 699
20.6 User Break Controller Stop Function................................................................................ 701
20.6.1 Transition to User Break Controller Stopped State.............................................. 701
20.6.2 Cancelling the User Break Controller Stopped State ........................................... 701
20.6.3 Examples of Stopping and Restarting the User Break Controller........................ 702
Section 21 Hitachi User Debug Interface (H-UDI)
21.1 Overview........................................................................................................................... 703
21.1.1 Features................................................................................................................ 703
21.1.2 Block Diagram..................................................................................................... 703
21.1.3 Pin Configuration................................................................................................. 705
21.1.4 Register Configuration......................................................................................... 706
21.2 Register Descriptions ........................................................................................................ 707
21.2.1 Instruction Register (SDIR) ................................................................................. 707
21.2.2 Data Register (SDDR) ......................................................................................... 708
..................................................................... 677
................................................... 703
Rev. 4.0, 04/00, page xix of 20