Pcmcia Interface - Hitachi SH7750 series Hardware Manual

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(SA: IO ← memory)

PCMCIA Interface

In the SH7750 Series (SH7750 and SH7750S), setting the A56PCM bit in BCR1 to 1 makes the

bus interface for external space areas 5 and 6 an IC memory card interface or I/O card interface as

stipulated in JEIDA specification version 4.2 (PCMCIA2.1).

Figure 13.44 shows an example of PCMCIA card connection to the SH7750 Series. To enable

active insertion of the PCMCIA cards (i.e. insertion or removal while system power is being

supplied), a 3-state buffer must be connected between the SH7750 Series' bus interface and the

PCMCIA cards.

As operation in big-endian mode is not explicitly stipulated in the JEIDA/PCMCIA specifications,

the SH7750 Series supports only a little-endian mode PCMCIA interface.

In the SH7750, the PCMCIA interface can only be accessed when the MMU is used. PCMCIA

memory space can be set in page units and there is a choice of 8-bit common memory, 16-bit

common memory, 8-bit attribute memory, 16-bit attribute memory, 8-bit I/O space, 16-bit I/O

space, or dynamic bus sizing, according to the accessed SA2 to SA0 bits.

The setting for wait cycles during a bus access can also be made in MMU page units. When the

accessed TC bit is cleared to 0, bits A5W2 to A5W0 in wait control register 2 (WCR2), and bits

A5PCW1 and A5PCW0, A5TED2 to A5TED0, and A5TEH2 to A5TEH0 in the PCMCIA control

control register 2 (WCR2), and bits A6PCW1 and A6PCW0, A6TED2 to A6TED0, and A6TEH2

Figure 13.43 Burst ROM Wait Access Timing

Rev. 4.0, 04/00, page 377 of 850

Sh7750sSh7750