Hitachi SH7750 series Hardware Manual page 365

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independently for areas 2 and 3 by means of bits A2W2–A2W0 and A3W2–A3W0 in WCR2.

This number of cycles corresponds to the number of synchronous DRAM CAS latency cycles.

Precharge-sel

(SA: IO ← memory)

Figure 13.26 Basic Timing for Synchronous DRAM Burst Read

In a synchronous DRAM cycle, the %6 signal is asserted for one cycle at the start of the data

transfer cycle corresponding to the READ or READA command. The order of access is as

follows: in a fill operation in the event of a cache miss, 64-bit boundary data including the missed

data is read first, then 16-byte boundary data including the missed data is read in wraparound

mode. The remaining 16 bytes of the 32-byte boundary data are read by the READA command

issued next.

Rev. 4.0, 04/00, page 354 of 850

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