Hitachi SH7750 series Hardware Manual page 819

1/2V
Note: When clock is input from TCK pin
SCK2/
/
BRKACK
TCK
TDI
TMS
TDO
t
TCKH
V
IH
DDQ
Figure 23.67 TCK Input Timing
t t
ASEBRKS ASEBRKH
Figure 23.68 Reset Hold Timing
t t
TDIS TDIH
Figure 23.69 H-UDI Data Transfer Timing
Figure 23.70 Pin Break Timing
t
TCKcyc
t
TCKL
V
IH
V
IL
t
TCKf
t
TCKcyc
t
PINBRK
V
IH
1/2V
DDQ
V
IL
t
TCKr
t
t
ASEBRKS
ASEBRKH
t
TDO
Rev. 4.0, 04/00, page 811 of 850