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19.1.3
Pin Configuration
Table 19.1 shows the INTC pin configuration.
Table 191
INTC Pins
Pin Name
Nonmaskable interrupt
input pin
Interrupt input pins
19.1.4
Register Configuration
The INTC has the registers shown in table 19.2.
Table 19.2 INTC Registers
Name
Interrupt control
register
Interrupt priority
register A
Interrupt priority
register B
Interrupt priority
register C
Interrupt priority
register D
Notes: 1. Initialized by a power-on reset or manual reset.
2. H'8000 when the NMI pin is high, H'0000 when the NMI pin is low.
3. SH7750S only
Abbreviation
NMI
,5/6–,5/3
Abbreviation
R/W
ICR
R/W
IPRA
R/W
IPRB
R/W
IPRC
R/W
IPRD
R/W
I/O
Function
Input
Input of nonmaskable interrupt request
signal
Input
Input of interrupt request signals
(maskable by I3–I0 in SR)
Initial
1
Value*
P4 Address
2
*
H'FFD00000
H'0000
H'FFD00004
H'0000
H'FFD00008
H'0000
H'FFD0000C
H'DA74 H'FFD00010
Area 7
Address
H'1FD00000
H'1FD00004
H'1FD00008
H'1FD0000C
H'1FD00010
Rev. 4.0, 04/00, page 661 of 850
Access
Size
16
16
16
16
16
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