Table of Contents
Advertisement
Bit 14—High Impedance Control (HIZCNT): Specifies the state of the 5$6 and &$6 signals in
standby mode and when the bus is released.
Bit 14: HIZCNT
0
1
Bits 13 to 11—Area 0 Burst ROM Control (A0BST2–A0BST0): These bits specify whether
burst ROM interface is used in area 0. When burst ROM interface is used, they also specify the
number of accesses in a burst. If area 0 is an MPX interface area, these bits are ignored.
Bit 13: A0BST2
Bit 12: A0BST1
0
0
1
1
0
1
Rev. 4.0, 04/00, page 276 of 850
Description
The 5$6, 5$65, :(Q/&$6Q/DQMn, 5'/&$66/)5$0(, and 5'5 signals
go to high-impedance (High-Z) in standby mode and when the bus is
released
The 5$6, 5$65, :(Q/&$6Q/DQMn, 5'/&$66/)5$0(, and 5'5 signals
drive in standby mode and when the bus is released
Bit 11: A0BST0
0
1
0
1
0
1
0
1
Description
Area 0 is accessed as SRAM interface
Area 0 is accessed as burst ROM
interface (4 consecutive accesses)
Can be used with 8-, 16-, or 32-bit bus
width
Area 0 is accessed as burst ROM
interface (8 consecutive accesses)
Can be used with 8-, 16-, or 32-bit bus
width
Area 0 is accessed as burst ROM
interface (16 consecutive accesses)
Can only be used with 8- or 16-bit bus
width. Do not specify for 32-bit bus width
Area 0 is accessed as burst ROM
interface (32 consecutive accesses)
Can only be used with 8-bit bus width
Reserved
Reserved
Reserved
(Initial value)
(Initial value)
Advertisement
Table of Contents
