Hitachi SH7750 series Hardware Manual page 725

Table 22.1 Pin Functions (cont)
Pin
No. No. Pin Name
%$&./
61 U3
%65(4
%5(4/
62 V3
%6$&.
63 W2 D8
64 Y2 D7
65 W3 CKE
66 V5 VDDQ
67 U5 VSSQ
:(8/&$68/
68 Y3
DQM5
:(7/&$67/
69 W4
DQM4
:(4/&$64/
70 Y4
DQM1
:(3/&$63/
71 W5
DQM0
72 Y5 A17
73 V6 VDDQ
74 U6 VSSQ
75 W6 A16
76 Y6 A15
77 V7 VDD
78 U7 VSS
79 W7 A14
80 Y7 A13
81 V8 VDDQ
82 U8 VSSQ
83 V4 NC
84 W8 A12
85 Y8 A11
86 W9 A10
I/O Function
O Bus
acknowledge/
bus request
I Bus
request/bus
acknowledge
I/O Data
I/O Data
O Clock output
enable
Power IO VDD (3.3 V)
Power IO GND (0 V)
O D47–D40
select signal
O D39–D32
select signal
O D15–D8 select
signal
O D7–D0 select
signal
O Address
Power IO VDD (3.3 V)
Power IO GND (0 V)
O Address
O Address
Power Internal VDD
(1.8 V)
Power Internal GND
(0 V)
O Address
O Address
Power IO VDD (3.3 V)
Power IO GND (0 V)
O Address
O Address
O Address
SRAM DRAM
Reset
:(8 &$68
:(7 &$67
:(4 &$64
:(3 &$63
Memory Interface
SDRAM PCMCIA MPX
CKE
DQM5
DQM4
:(4
DQM1
DQM0
Rev. 4.0, 04/00, page 717 of 850
A8
A7