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DMAIW2/AnIW2
0
1
• Idle Insertion between Accesses
Read
Preceding
Cycle
CPU DMA
Read
Write
DMA read
(memory →
device)
DMA write
D
(device →
memory)
M, D: WCR1 wait insertion
(One cycle inserted in MPX access even if WCR1 is cleared to 0)
M:
Memory setting (area 0 to area 6)
D:
DMA setting
No insertion in consecutive accesses to same device
*:
Note: When synchronous DRAM is used in RAS down mode, set bits DMAIW2–DMAIW0 to 000
and bits A3IW2–A3IW0 to 000.
13.2.4
Wait Control Register 2 (WCR2)
Wait control register 2 (WCR2) is a 32-bit readable/writable register that specifies the number of
wait states to be inserted for each area. It also specifies the data access pitch when performing
burst memory access. This enables low-speed memory to be connected without using external
circuitry.
DMAIW1/AnIW1
0
1
0
1
Following Cycle
Same Area
Write
CPU DMA
M
M
M
M
D
D
D*
DMAIW0/AnIW0
0
1
0
1
0
1
0
1
Different Area
Read
CPU DMA
CPU DMA
M
M
M
M
M
M
M
M
M
D
D
D
Inserted Idle Cycles
0
1
2
3
6
9
12
15
Same
Area
Write
MPX
Address
Output
M
M (1)
M
M
—
D
—
Rev. 4.0, 04/00, page 283 of 850
(Initial value)
Different
Area
MPX
Address
Output
M (1)
M (1)
M (1)
D (1)
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