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(a) DMAC Normal Mode
Table 14.8 shows the memory interfaces that can be specified for the transfer source and transfer
destination in DMA transfer initiated by an external request supported by the SH7750 Series in
DMAC normal mode.
Table 14.8 External Request Transfer Sources and Destinations in Normal Mode
Transfer Direction (Settable Memory Interface)
Transfer Source
1
Synchronous DRAM
2
External device with DACK
3
SRAM-type, DRAM
4
External device with DACK
5
Synchronous DRAM
6
SRAM-type, MPX, PCMCIA
7
SRAM-type, DRAM, PCMCIA,
MPX
8
SRAM-type, MPX, PCMCIA
"SRAM-type" in the table indicates an SRAM, byte control SRAM, or burst ROM setting.
Notes: 1. Memory interfaces on which transfer is possible in single address mode are SRAM,
byte control SRAM, burst ROM, DRAM, and synchronous DRAM.
2. When performing dual address mode transfer, make the DACK output setting for the
SRAM, byte control SRAM, burst ROM, PCMCIA, or MPX interface.
(b) DDT Mode
Table 14.9 shows the memory interfaces that can be specified for the transfer source and transfer
destination in DMA transfer initiated by an external request supported by the SH7750 Series in
DDT mode.
Rev. 4.0, 04/00, page 454 of 850
Transfer Destination
External device with DACK
Synchronous DRAM
External device with DACK
SRAM-type, DRAM
SRAM-type, MPX, PCMCIA
*
Synchronous DRAM
SRAM-type, MPX, PCMCIA
*
SRAM-type, DRAM, PCMCIA,
MPX
*: DACK output setting in dual address mode transfer
Usable
Address
DMAC
Mode
Channels
Single
0, 1
Single
0, 1
Single
0, 1
Single
0, 1
*
Dual
0, 1
Dual
0, 1
*
Dual
0, 1
Dual
0, 1
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