Addressing Modes - Hitachi SH7750 series Hardware Manual

7.2

Addressing Modes

Addressing modes and effective address calculation methods are shown in table 7.1. When a
location in virtual memory space is accessed (MMUCR.AT = 1), the effective address is translated
into a physical memory address. If multiple virtual memory space systems are selected
(MMUCR.SV = 0), the least significant bit of PTEH is also referenced as the access ASID. See
section 3, Memory Management Unit (MMU).
Table 7.1 Addressing Modes and Effective Addresses
Addressing Instruction
Mode Format
Register Rn
direct
Register @Rn
indirect
Register @Rn+
indirect
with post-
increment
Register @–Rn
indirect
with pre-
decrement
Effective Address Calculation Method
Effective address is register Rn.
(Operand is register Rn contents.)
Effective address is register Rn contents.
Rn
Effective address is register Rn contents.
A constant is added to Rn after instruction
execution: 1 for a byte operand, 2 for a word
operand, 4 for a longword operand, 8 for a
quadword operand.
Rn
Rn + 1/2/4/8
1/2/4/8
Effective address is register Rn contents,
decremented by a constant beforehand:
1 for a byte operand, 2 for a word operand,
4 for a longword operand, 8 for a quadword
operand.
Rn
Rn – 1/2/4/8
1/2/4/8
Rn
Rn
+
–
Rn – 1/2/4/8
Rev. 4.0, 04/00, page 131 of 850
Calculation
Formula
—
Rn → EA
(EA: effective
address)
Rn → EA
After
instruction
execution
Byte:
Rn + 1 → Rn
Word:
Rn + 2 → Rn
Longword:
Rn + 4 → Rn
Quadword:
Rn + 8 → Rn
Byte:
Rn – 1 → Rn
Word:
Rn – 2 → Rn
Longword:
Rn – 4 → Rn
Quadword:
Rn – 8 → Rn
Rn → EA
(Instruction
executed
with Rn after
calculation)