Hitachi SH7750 series Hardware Manual page 802

CKIO
A25–A0
RD/
D63–D0
(write)
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
Figure 23.49 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (TRAS = 0, TRC = 1)
Rev. 4.0, 04/00, page 794 of 850
TRr1 TRr2 TRr3
t
AD
t
CSD
t
RWD
t
t
RASD
RASD
t
CASD1
t
CASD1
t
WDD
t
DACD
t
DACD
TRr4 TRr5 Trc
t
RASD
t
CASD1
Trc
Trc