Hitachi SH7750 series Hardware Manual page 832

&.,25(1% &.,25(1%
&.,25(1% &.,25(1%
Description
5'5, RD/:55, and CKIO2 have the same pin states as 5', RD/:5, and
0
CKIO, respectively
5'5, RD/:55, and CKIO2 are in the high-impedance state
1
Note: CKIO is fed back to PLL2 to coordinate the external clock and internal clock phases.
However, CKIO2 is not fed back.
Rev. 4.0, 04/00, page 825 of 850